Cross Reference: /external/vixl/src/aarch64/assembler-aarch64.cc

Lines Matching refs:CPURegister
946 void Assembler::ldp(const CPURegister& rt,
947                     const CPURegister& rt2,
953 void Assembler::stp(const CPURegister& rt,
954                     const CPURegister& rt2,
968 void Assembler::LoadStorePair(const CPURegister& rt,
969                               const CPURegister& rt2,
997 void Assembler::ldnp(const CPURegister& rt,
998                      const CPURegister& rt2,
1004 void Assembler::stnp(const CPURegister& rt,
1005                      const CPURegister& rt2,
1011 void Assembler::LoadStorePairNonTemporal(const CPURegister& rt,
1012                                          const CPURegister& rt2,
1083 void Assembler::ldr(const CPURegister& rt,
1092 void Assembler::str(const CPURegister& rt,
1165 void Assembler::ldur(const CPURegister& rt,
1174 void Assembler::stur(const CPURegister& rt,
1200 void Assembler::ldr(const CPURegister& rt, RawLiteral* literal) {
1211 void Assembler::ldr(const CPURegister& rt, int64_t imm19) {
4310 void Assembler::LoadStore(const CPURegister& rt,
4626 LoadStoreOp Assembler::LoadOpFor(const CPURegister& rt) {
4649 LoadStoreOp Assembler::StoreOpFor(const CPURegister& rt) {
4672 LoadStorePairOp Assembler::StorePairOpFor(const CPURegister& rt,
4673                                           const CPURegister& rt2) {
4693 LoadStorePairOp Assembler::LoadPairOpFor(const CPURegister& rt,
4694                                          const CPURegister& rt2) {
4702     const CPURegister& rt, const CPURegister& rt2) {
4723     const CPURegister& rt, const CPURegister& rt2) {
4730 LoadLiteralOp Assembler::LoadLiteralOpFor(const CPURegister& rt) {
4748 bool AreAliased(const CPURegister& reg1,
4749                 const CPURegister& reg2,
4750                 const CPURegister& reg3,
4751                 const CPURegister& reg4,
4752                 const CPURegister& reg5,
4753                 const CPURegister& reg6,
4754                 const CPURegister& reg7,
4755                 const CPURegister& reg8) {
4762   const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
4787 bool AreSameSizeAndType(const CPURegister& reg1,
4788                         const CPURegister& reg2,
4789                         const CPURegister& reg3,
4790                         const CPURegister& reg4,
4791                         const CPURegister& reg5,
4792                         const CPURegister& reg6,
4793                         const CPURegister& reg7,
4794                         const CPURegister& reg8) {