Cross Reference: /system/core/libpixelflinger/codeflinger/MIPSAssembler.cpp

Lines Matching defs:value
227     // ALOGW("immediate value %08x at pc %08x\n", immediate, (int)pc());
228     amode.value = immediate;
236     amode.value = shift;
261     amode.value = immed12;
272     amode.value = immed12;
283     // amode.value = shift;
315     amode.value = immed8;
342 // would be overwritten by this instruction. If so, move the value to a
345 // instruction will _also_ use this value (a defect of the simple 1-pass, one-
347 // save the value before it is overwritten. This costs an extra MOVE instr.
377         if ((!_signed && amode.value > 0xffff)
378                 || (_signed && ((int)amode.value < -32768 || (int)amode.value > 32767) )) {
379             mMips->LUI(tmpReg, (amode.value >> 16));
380             if (amode.value & 0x0000ffff) {
381                 mMips->ORI(tmpReg, tmpReg, (amode.value & 0x0000ffff));
386             source = amode.value;
391             case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break;
392             case LSR: mMips->SRL(tmpReg, amode.reg, amode.value); break;
393             case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break;
395                           mMips->ROTR(tmpReg, amode.reg, amode.value);
397                           mMips->RORIsyn(tmpReg, amode.reg, amode.value);
492             if (amode.value > 0xffff) {
493                 mMips->LUI(Rd, (amode.value >> 16));
494                 if (amode.value & 0x0000ffff) {
495                     mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
498                 mMips->ORI(Rd, 0, amode.value);
502             case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
503             case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
504             case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
506                           mMips->ROTR(Rd, amode.reg, amode.value);
508                           mMips->RORIsyn(Rd, amode.reg, amode.value);
524             if (amode.value > 0xffff) {
525                 mMips->LUI(Rd, (amode.value >> 16));
526                 if (amode.value & 0x0000ffff) {
527                     mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
530                 mMips->ORI(Rd, 0, amode.value);
534             case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
535             case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
536             case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
538                           mMips->ROTR(Rd, amode.reg, amode.value);
540                           mMips->RORIsyn(Rd, amode.reg, amode.value);
769             amode.value = 0;
776             mMips->LW(Rd, Rn, amode.value);
778                 mMips->ADDIU(Rn, Rn, amode.value);
786             mMips->ADDIU(Rn, Rn, amode.value);
803             amode.value = 0;
807             mMips->LBU(Rd, Rn, amode.value);
809                 mMips->ADDIU(Rn, Rn, amode.value);
814             mMips->ADDIU(Rn, Rn, amode.value);
832             amode.value = 0;
842                 mMips->ADDIU(Rn, Rn, amode.value);
845                 // No writeback so store offset by value
846                 mMips->SW(Rd, Rn, amode.value);
851             mMips->ADDIU(Rn, Rn, amode.value);  // post index always writes back
868             amode.value = 0;
872             mMips->SB(Rd, Rn, amode.value);
874                 mMips->ADDIU(Rn, Rn, amode.value);
879             mMips->ADDIU(Rn, Rn, amode.value);
896             amode.value = 0;
899             mMips->LHU(Rd, Rn, amode.value);
903             mMips->ADDIU(Rn, Rn, amode.value);
940             amode.value = 0;
943             mMips->SH(Rd, Rn, amode.value);
947             mMips->ADDIU(Rn, Rn, amode.value);
1415     char value[PROPERTY_VALUE_MAX];
1416     value[0] = '\0';
1418     property_get("debug.pf.disasm", value, "0");
1420     if (atoi(value) != 0) {