Cross Reference: /system/core/libunwindstack/tests/ElfInterfaceArmTest.cpp

Lines Matching refs:regs
314   RegsArm regs;
315   regs[ARM_REG_SP] = 0x1000;
316   regs[ARM_REG_LR] = 0x20000;
317   regs.set_sp(regs[ARM_REG_SP]);
318   regs.set_pc(0x1234);
319   ASSERT_FALSE(interface.StepExidx(0x7000, 0, &regs, &process_memory_, &finished));
325   ASSERT_FALSE(interface.StepExidx(0x7000, 0, &regs, &process_memory_, &finished));
330   ASSERT_TRUE(interface.StepExidx(0x7000, 0, &regs, &process_memory_, &finished));
333   ASSERT_EQ(0x1000U, regs.sp());
334   ASSERT_EQ(0x1000U, regs[ARM_REG_SP]);
335   ASSERT_EQ(0x20000U, regs.pc());
336   ASSERT_EQ(0x20000U, regs[ARM_REG_PC]);
339   ASSERT_TRUE(interface.StepExidx(0x8000, 0x1000, &regs, &process_memory_, &finished));
343   ASSERT_FALSE(interface.StepExidx(0x8000, 0x9000, &regs, &process_memory_, &finished));
357   RegsArm regs;
358   regs[ARM_REG_SP] = 0x10000;
359   regs[ARM_REG_LR] = 0x20000;
360   regs.set_sp(regs[ARM_REG_SP]);
361   regs.set_pc(0x1234);
365   ASSERT_TRUE(interface.StepExidx(0x7000, 0, &regs, &process_memory_, &finished));
368   ASSERT_EQ(0x10004U, regs.sp());
369   ASSERT_EQ(0x10004U, regs[ARM_REG_SP]);
370   ASSERT_EQ(0x10U, regs.pc());
371   ASSERT_EQ(0x10U, regs[ARM_REG_PC]);
382   RegsArm regs;
383   regs[ARM_REG_SP] = 0x10000;
384   regs[ARM_REG_LR] = 0x20000;
385   regs.set_sp(regs[ARM_REG_SP]);
386   regs.set_pc(0x1234);
389   ASSERT_TRUE(interface.StepExidx(0x7000, 0, &regs, &process_memory_, &finished));
392   ASSERT_EQ(0x10000U, regs.sp());
393   ASSERT_EQ(0x10000U, regs[ARM_REG_SP]);
394   ASSERT_EQ(0x1234U, regs.pc());
405   RegsArm regs;
406   regs[ARM_REG_SP] = 0x10000;
407   regs[ARM_REG_LR] = 0x20000;
408   regs.set_sp(regs[ARM_REG_SP]);
409   regs.set_pc(0x1234);
412   ASSERT_TRUE(interface.StepExidx(0x7000, 0, &regs, &process_memory_, &finished));
415   ASSERT_EQ(0x10000U, regs.sp());
416   ASSERT_EQ(0x10000U, regs[ARM_REG_SP]);
417   ASSERT_EQ(0x1234U, regs.pc());
432   RegsArm regs;
433   regs[ARM_REG_SP] = 0x10000;
434   regs[ARM_REG_LR] = 0x20000;
435   regs.set_sp(regs[ARM_REG_SP]);
436   regs.set_pc(0x1234);
439   ASSERT_TRUE(interface.StepExidx(0x7000, 0, &regs, &process_memory_, &finished));
442   ASSERT_EQ(0U, regs.pc());
447   regs[ARM_REG_SP] = 0x10000;
448   regs[ARM_REG_LR] = 0x20000;
449   regs.set_sp(regs[ARM_REG_SP]);
450   regs.set_pc(0x1234);
452   ASSERT_TRUE(interface.StepExidx(0x7000, 0, &regs, &process_memory_, &finished));
455   ASSERT_EQ(0U, regs.pc());