Searched defs:CRm (Results 1 - 7 of 7) sorted by relevance

/external/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
98 Ops[4].getAsInteger(10, CRm);
100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
110 uint32_t CRm = (Bits >> 3) & 0xf; local
114 utostr(CRm) + "_" + utostr(Op2);
/external/capstone/arch/AArch64/
H A DAArch64BaseInfo.c633 uint32_t Op0, Op1, CRn, CRm, Op2; local
671 CRm = (Bits >> 3) & 0xf;
687 CRmS = utostr(CRm, false);
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h2817 static Instr CRm(int imm4) { function in class:vixl::aarch64::Assembler
/external/capstone/arch/ARM/
H A DARMDisassembler.c5095 unsigned CRm = fieldFromInstruction_4(Val, 0, 4); local
5113 MCOperand_CreateImm0(Inst, CRm);
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp5273 unsigned CRm = fieldFromInstruction(Val, 0, 4); local
5292 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5293 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5309 Inst.addOperand(MCOperand::createImm(CRm));
/external/clang/lib/CodeGen/
H A DCGBuiltin.cpp4038 Value *CRm = EmitScalarExpr(E->getArg(3)); local
4045 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm});
4064 Value *CRm = EmitScalarExpr(E->getArg(2)); local
4065 Value *RtAndRt2 = Builder.CreateCall(F, {Coproc, Opc1, CRm});
/external/valgrind/VEX/priv/
H A Dguest_arm64_toIR.c7114 11010 10100 0 00 011 0011 CRm 1 01 11111 DMB opt
7115 11010 10100 0 00 011 0011 CRm 1 00 11111 DSB opt
7116 11010 10100 0 00 011 0011 CRm 1 10 11111 ISB opt
7123 UInt CRm = INSN(11,8); local
7124 vassert(opc <= 2 && CRm <= 15);
7131 DIP("%s %s\n", opNames[opc], howNames[CRm]);
7187 1101 0101 0000 0011 0011 m 0101 1111 CLREX CRm
7188 CRm is apparently ignored.

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