Searched defs:DstR (Results 1 - 5 of 5) sorted by relevance
/external/llvm/lib/Target/Hexagon/ |
H A D | RDFCopy.cpp | 35 RegisterRef DstR = { Dst.getReg(), Dst.getSubReg() }; local 37 if (TargetRegisterInfo::isVirtualRegister(DstR.Reg)) { 41 if (MRI.getRegClass(DstR.Reg) != MRI.getRegClass(SrcR.Reg)) 43 } else if (TargetRegisterInfo::isPhysicalRegister(DstR.Reg)) { 47 if (TRI.getMinimalPhysRegClass(DstR.Reg) != 54 EM.insert(std::make_pair(DstR, SrcR)); 86 // Insert DstR into the map.
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H A D | HexagonSplitDouble.cpp | 965 unsigned DstR = MI->getOperand(0).getReg(); local 966 if (MRI->getRegClass(DstR) == DoubleRC) {
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H A D | HexagonExpandCondsets.cpp | 250 MachineBasicBlock::iterator At, unsigned DstR, 608 /// destination register DstR:DstSR, and using the predicate register from 613 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, 628 .addReg(DstR, State, DstSR) 611 genCondTfrFor(MachineOperand &SrcOp, MachineBasicBlock::iterator At, unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, bool PredSense, bool ReadUndef, bool ImpUse) argument
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H A D | HexagonFrameLowering.cpp | 1380 unsigned DstR = MI->getOperand(0).getReg(); local 1382 if (!Hexagon::ModRegsRegClass.contains(DstR) || 1389 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR) 1435 unsigned DstR = MI->getOperand(0).getReg(); local 1447 // DstR = C2_tfrrp TmpR if DstR is a predicate register 1448 // DstR = A2_tfrrcr TmpR if DstR is a modifier register 1451 BuildMI(B, It, DL, HII.get(TfrOpc), DstR) 1507 unsigned DstR local 1603 unsigned DstR = MI->getOperand(0).getReg(); local 1691 unsigned DstR = MI->getOperand(0).getReg(); local 2151 unsigned DstR = MI->getOperand(0).getReg(); local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FixupLEAs.cpp | 346 const unsigned DstR = MI.getOperand(0).getReg(); local 349 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR)) 377 const MachineOperand &Src1 = MI.getOperand(SrcR1 == DstR ? 1 : 3); 378 const MachineOperand &Src2 = MI.getOperand(SrcR1 == DstR ? 3 : 1); 388 const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3);
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