Searched defs:HiReg (Results 1 - 10 of 10) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/Mips/
H A DMipsExpandPseudo.cpp89 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); local
98 BuildMI(MBB, I, dl, Mtc1Tdd, *(SubReg + 1)).addReg(HiReg);
/external/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp783 unsigned HiReg = HiOperand.getReg(); local
791 .addReg(HiReg, HiRegKillFlag)
799 .addReg(HiReg, HiRegKillFlag)
821 // DoubleRegDest = combine HiReg, #LoImm
823 .addReg(HiReg, HiRegKillFlag)
834 unsigned HiReg = HiOperand.getReg(); local
840 // DoubleRegDest = combine HiReg, LoReg
842 .addReg(HiReg, HiRegKillFlag)
H A DHexagonFrameLowering.cpp826 unsigned HiReg = HRI.getSubReg(Reg, Hexagon::subreg_hireg); local
828 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
/external/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp285 unsigned HiReg = I->getOperand(2).getReg(); local
301 std::swap(LoReg, HiReg);
304 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC,
H A DMipsSEInstrInfo.cpp651 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); local
696 .addReg(HiReg);
701 .addReg(HiReg);
/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2184 unsigned SrcReg, LoReg, HiReg; local
2189 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2193 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2197 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2201 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2204 SrcReg = X86::EDX; LoReg = HiReg = 0;
2207 SrcReg = X86::RDX; LoReg = HiReg = 0;
2268 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2302 assert(HiReg && "Register for high half is not defined!");
2303 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NV
2341 unsigned LoReg, HiReg, ClrReg; local
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1884 unsigned LoReg, HiReg; local
1887 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
1888 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
1889 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
1890 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
1921 if (HiReg == X86::AH && Subtarget->is64Bit() &&
1951 HiReg, NVT, InFlag);
1984 unsigned LoReg, HiReg, ClrReg; local
1989 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
1994 LoReg = X86::AX; HiReg
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp3962 // 'false' otherwise. If Reg is in the register list or is HiReg, set
3965 unsigned HiReg, bool &containsReg) {
3972 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3964 checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg) argument
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp6099 // 'false' otherwise. If Reg is in the register list or is HiReg, set
6102 unsigned Reg, unsigned HiReg,
6110 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
6101 checkLowRegisterList(const MCInst &Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg) argument
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp9054 unsigned HiReg = MI.getOperand(1).getReg(); local
9056 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
9063 .addReg(HiReg).addReg(ReadAgainReg);

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