| /external/llvm/lib/Analysis/ |
| H A D | ScalarEvolutionNormalization.cpp | 215 const SCEV *RO = X->getRHS(); local
217 const SCEV *RN = TransformSubExpr(RO, User, OperandValToReplace);
218 if (LO != LN || RO != RN)
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| /external/python/cpython2/Include/ |
| H A D | structmember.h | 81 #define RO READONLY /* Shorthand */ macro
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| /external/swiftshader/third_party/LLVM/lib/Analysis/ |
| H A D | ScalarEvolutionNormalization.cpp | 185 const SCEV *RO = X->getRHS(); local
187 const SCEV *RN = TransformSubExpr(RO, User, OperandValToReplace);
188 if (LO != LN || RO != RN)
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| /external/autotest/client/common_lib/cros/ |
| H A D | cr50_utils.py | 12 RO = 'ro' variable
27 # 'fwver' is used to get the running RO and RW versions from cr50
28 # 'binvers' gets the version strings for each RO and RW region in the given
42 # keyids: RO 0xaa66150f, RW 0xde88588d
43 # offsets: backup RO at 0x40000, backup RW at 0x44000
45 # RO 0.0.10
141 the version from versions or "-1.-1.-1" if an invalid RO was detected.
171 ro = GetVersion(versions, RO)
301 """Combine the RO and RW tuple into a understandable string"""
302 return 'RO
[all...] |
| /external/llvm/include/llvm/ExecutionEngine/Orc/ |
| H A D | CompileOnDemandLayer.h | 87 typedef ResourceOwnerImpl<ResourceT, ResourcePtrT> RO; typedef
88 return llvm::make_unique<RO>(std::move(ResourcePtr));
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 361 OrderedRegisterList(const RegisterOrdering &RO) : Ord(RO) {} argument
483 void buildOrderingMF(RegisterOrdering &RO) const;
484 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const;
551 void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const {
567 RO.insert(std::make_pair(R, Index++));
579 RegisterOrdering &RO) const {
591 RO.insert(std::make_pair(VRs[i], i));
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| H A D | HexagonEarlyIfConv.cpp | 783 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1); local
785 SR = RO.getReg(), SSR = RO.getSubReg();
787 TR = RO.getReg(), TSR = RO.getSubReg();
789 FR = RO.getReg(), FSR = RO.getSubReg();
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| H A D | HexagonExpandCondsets.cpp | 265 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
913 /// In the range [First, Last], rename all references to the "old" register RO
916 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN, argument
930 if (!Op.isReg() || RO != RegisterRef(Op))
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| H A D | HexagonInstrInfo.cpp | 628 const MachineOperand &RO = Cond[1]; local
629 unsigned Flags = getUndefRegState(RO.isUndef());
630 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
651 const MachineOperand &RO = Cond[1]; local
652 unsigned Flags = getUndefRegState(RO.isUndef());
653 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
|
| /external/llvm/tools/llvm-diff/ |
| H A D | DifferenceEngine.cpp | 354 Value *LO = L->getOperand(I), *RO = R->getOperand(I); local
355 if (!equivalentAsOperands(LO, RO)) {
356 if (Complain) Engine.logf("operands %l and %r differ") << LO << RO; local
|
| /external/swiftshader/third_party/LLVM/tools/llvm-diff/ |
| H A D | DifferenceEngine.cpp | 354 Value *LO = L->getOperand(I), *RO = R->getOperand(I); local
355 if (!equivalentAsOperands(LO, RO)) {
356 if (Complain) Engine.logf("operands %l and %r differ") << LO << RO; local
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| H A D | AsmWriterEmitter.cpp | 858 const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i]; local
860 switch (RO.Kind) {
863 const Record *Rec = RO.getRecord();
864 StringRef ROName = RO.getName();
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| /external/llvm/utils/TableGen/ |
| H A D | AsmWriterEmitter.cpp | 826 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i]; local
828 switch (RO.Kind) {
830 const Record *Rec = RO.getRecord();
831 StringRef ROName = RO.getName();
912 MIOpNum += RO.getMINumOperands();
|
| /external/deqp/framework/common/ |
| H A D | tcuCompressedTexture.cpp | 671 const deUint8 RO = extend6To8((deUint8)getBits(src, 57, 62)); local
687 const int unclampedR = (x * ((int)RH-(int)RO) + y * ((int)RV-(int)RO) + 4*(int)RO + 2) >> 2;
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| /external/swiftshader/src/Renderer/ |
| H A D | ETC_Decoder.cpp | 282 unsigned char RO : 6; member in struct:__anon22344::ETC2::__anon22345::__anon22346::__anon22355
564 int ro = extend_6to8bits(RO);
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| H A D | RegionStore.cpp | 114 const RegionOffset &RO = R->getAsOffset(); local
115 if (RO.hasSymbolicOffset())
116 return BindingKey(cast<SubRegion>(R), cast<SubRegion>(RO.getRegion()), k);
118 return BindingKey(RO.getRegion(), RO.getOffset(), k);
1102 const RegionOffset &RO = baseR->getAsOffset(); local
1104 if (RO.hasSymbolicOffset()) {
1112 uint64_t LowerOffset = RO.getOffset();
|
| /external/python/cpython3/Lib/test/ |
| H A D | test_enum.py | 1719 RO = 0 variable in class:TestFlag.Open
1741 self.assertEqual(str(Open.RO), 'Open.RO')
1744 self.assertEqual(str(Open.RO | Open.CE), 'Open.CE')
1746 self.assertEqual(str(~Open.RO), 'Open.CE|AC|RW|WO')
1749 self.assertEqual(str(~(Open.RO | Open.CE)), 'Open.AC')
1768 self.assertEqual(repr(Open.RO), '<Open.RO: 0>')
1771 self.assertEqual(repr(Open.RO | Open.CE), '<Open.CE: 524288>')
1773 self.assertEqual(repr(~Open.RO), '<Ope
2040 RO = 0 variable in class:TestIntFlag.Open
[all...] |