| /external/capstone/arch/AArch64/ |
| H A D | AArch64Disassembler.c | 1195 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); local
1241 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1250 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1259 Rt == Rt2)
1271 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); local
1329 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1342 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1353 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1364 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1375 DecodeFPR32RegisterClass(Inst, Rt2, Add
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 1086 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); local
1140 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1149 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1158 Rt == Rt2)
1169 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); local
1228 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1241 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1252 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1263 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1274 DecodeFPR32RegisterClass(Inst, Rt2, Add
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 3911 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); local
3916 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3925 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3937 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); local
3942 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3947 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3991 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); local
4001 if (writeback && (Rn == Rt || Rn == Rt2))
4003 if (Rt == Rt2)
4009 // Rt2
4028 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); local
[all...] |
| /external/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 2615 static Instr Rt2(CPURegister rt2) { function in class:vixl::aarch64::Assembler
|
| /external/capstone/arch/ARM/ |
| H A D | ARMDisassembler.c | 1677 unsigned Rt2 = Rt + 1; local
1701 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1705 if (Rt2 == 15)
1724 if (Rt2 == 15)
1730 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1734 if (writeback && (Rn == Rt || Rn == Rt2))
4800 unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); local
4805 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4814 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Addres
4827 unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); local
4875 unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); local
4912 unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); local
4975 unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4); local
5099 unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4); local
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1633 unsigned Rt2 = Rt + 1; local
1657 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1661 if (Rt2 == 15)
1680 if (Rt2 == 15)
1686 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1690 if (writeback && (Rn == Rt || Rn == Rt2))
4931 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); local
4936 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Addres
4957 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); local
5004 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); local
5041 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); local
5099 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); local
5277 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); local
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2805 // Rt, Rt2
2825 // Rt, Rt2
3022 // Rt, Rt2
3042 // Rt, Rt2
4044 // Rt2 must be Rt + 1.
4046 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); local
4047 if (Rt2 != Rt + 1)
4053 // Rt2 must be Rt + 1.
4055 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); local
4056 if (Rt2 !
4066 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); local
[all...] |
| /external/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 4029 // the intrinsic has 4 because Rt and Rt2
4042 Value *Rt2 = Builder.CreateLShr(RtAndRt2, C1); local
4043 Rt2 = Builder.CreateTruncOrBitCast(Rt2, Int32Ty);
4045 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm});
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 3442 // the Rt == Rt2. All of those are undefined behaviour.
3450 unsigned Rt2 = Inst.getOperand(2).getReg(); local
3455 if (RI->isSubRegisterEq(Rn, Rt2))
3467 unsigned Rt2 = Inst.getOperand(1).getReg(); local
3468 if (Rt == Rt2)
3469 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
3480 unsigned Rt2 = Inst.getOperand(2).getReg(); local
3481 if (Rt == Rt2)
3482 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
3496 unsigned Rt2 local
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 6042 unsigned Rt2 = MRI->getEncodingValue(Reg2); local
6044 // Rt2 must be Rt + 1 and Rt must be even.
6045 if (Rt + 1 != Rt2 || (Rt & 1)) {
6238 // Rt2 must be Rt + 1.
6239 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); local
6240 if (Rt2 != Rt + 1)
6248 if (Rn == Rt || Rn == Rt2)
6259 // Rt2 must be different from Rt.
6261 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); local
6262 if (Rt2
6278 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); local
6288 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); local
[all...] |