| /external/fec/ |
| H A D | encode_rs_8.c | 12 static enum {UNKNOWN=0,MMX,SSE,SSE2,ALTIVEC,PORT} cpu_mode; enumerator in enum:__anon7073
30 } else if(f & (1<<25)){ /* SSE is present */
31 cpu_mode = SSE;
59 case SSE:
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| H A D | fec.h | 261 extern enum cpu_mode {UNKNOWN=0,PORT,MMX,SSE,SSE2,ALTIVEC} Cpu_mode; enumerator in enum:cpu_mode
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| /external/swiftshader/src/Common/ |
| H A D | CPUID.hpp | 33 static bool supportsMMX2(); // MMX instructions added by SSE: pshufw, pmulhuw, pmovmskb, pavgw/b, pextrw, pinsrw, pmaxsw/ub, etc.
56 static bool SSE; member in class:sw::CPUID
98 return supportsSSE(); // Coincides with 64-bit integer vector instructions supported by SSE
103 return SSE && enableSSE;
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| H A D | CPUID.cpp | 34 bool CPUID::SSE = detectSSE(); member in class:sw::CPUID
199 return SSE = (registers[3] & 0x02000000) != 0;
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| /external/swiftshader/src/OpenGL/libGL/ |
| H A D | Display.cpp | 73 int SSE = false; local
74 size_t length = sizeof(SSE);
75 sysctlbyname("hw.optional.sse", &SSE, &length, 0, 0);
76 return SSE;
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| /external/libchrome/base/ |
| H A D | cpu.h | 22 SSE, enumerator in enum:base::CPU::IntelMicroArchitecture
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| /external/tensorflow/tensorflow/core/platform/ |
| H A D | cpu_info.h | 41 SSE = 1, enumerator in enum:tensorflow::port::CPUFeature
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| /external/mesa3d/src/gallium/drivers/swr/rasterizer/common/ |
| H A D | isa.hpp | 75 bool SSE(void) { return CPU_Rep.f_1_EDX_[25]; } function in class:InstructionSet
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| /external/eigen/Eigen/src/Core/util/ |
| H A D | Constants.h | 463 SSE = 0x1, enumerator in enum:Eigen::Architecture::Type
468 Target = SSE
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| /external/clang/lib/CodeGen/ |
| H A D | TargetInfo.cpp | 840 /// Returns true if this type can be passed in SSE registers with the
856 /// Returns true if this aggregate is small enough to be passed in SSE registers
1353 // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1853 SSE, enumerator in enum:__anon1658::X86_64ABIInfo::Class
1876 /// final MEMORY or SSE classes when necessary.
1954 /// GCC classifies <1 x long long> as SSE but compatibility with older clang
2255 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2259 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2271 if (AggregateSize > 128 && (Lo != SSE || H
[all...] |
| H A D | CGBuiltin.cpp | 6730 // AVX has a larger immediate than SSE we would need separate builtins to
6732 // SSE only builtin, this implements eight separate builtins to match gcc
6742 // TODO: The builtins could be removed if the SSE header files used vector
6766 SSE, enumerator in enum:X86Features
6798 .Case("sse", X86Features::SSE)
7265 // SSE packed comparison intrinsics
7295 // If this one of the SSE immediates, we can use native IR.
7332 // SSE scalar comparison intrinsics
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| /external/valgrind/VEX/priv/ |
| H A D | guest_s390_toIR.c | 15545 } SSE; member in union:__anon28064
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