Searched defs:Spill (Results 1 - 7 of 7) sorted by relevance

/external/llvm/lib/CodeGen/
H A DRegAllocBasic.cpp163 // Spill or split all live virtual registers currently unified under PhysReg
189 // Spill each interfering vreg allocated to PhysReg or an alias.
191 LiveInterval &Spill = *Intfs[i]; local
194 if (!VRM->hasPhys(Spill.reg))
199 Matrix->unassign(Spill);
201 // Spill the extracted interval.
202 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, nullptr, &DeadRemats);
H A DInlineSpiller.cpp123 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
125 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
973 /// spillAll - Spill all registers remaining after rematerialization.
992 // Spill around uses of all RegsToSpill.
1054 void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot, argument
1057 SlotIndex Idx = LIS.getInstructionIndex(Spill);
1060 MergeableSpills[MIdx].insert(&Spill);
1066 bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill, argument
1071 SlotIndex Idx = LIS.getInstructionIndex(Spill);
1074 return MergeableSpills[MIdx].erase(&Spill);
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/external/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp202 struct SpilledReg Spill; local
203 Spill.Lane = Lane;
210 return Spill;
222 Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
223 return Spill;
H A DSIRegisterInfo.cpp528 struct SIMachineFunctionInfo::SpilledReg Spill = local
531 if (Spill.hasReg()) {
534 Spill.VGPR)
536 .addImm(Spill.Lane);
542 // Spill SGPR to a frame index.
592 struct SIMachineFunctionInfo::SpilledReg Spill = local
595 if (Spill.hasReg()) {
599 .addReg(Spill.VGPR)
600 .addImm(Spill.Lane)
/external/v8/src/crankshaft/
H A Dlithium-allocator.cc1538 Spill(current);
1845 Spill(current);
1900 // Spill starting part of live range up to that use.
2089 Spill(second_part);
2120 Spill(second_part);
2130 void LAllocator::Spill(LiveRange* range) { function in class:LAllocator
/external/swiftshader/third_party/subzero/src/
H A DIceTargetLoweringX86BaseImpl.h3147 Variable *Spill = Func->makeVariable(IceType_f64); local
3148 Spill->setLinkedTo(Src0Var);
3149 Spill->setMustNotHaveReg();
3150 _movq(Spill, Src0RM);
3151 SpillLo = Traits::VariableSplit::create(Func, Spill,
3153 SpillHi = Traits::VariableSplit::create(Func, Spill,
3193 Variable *Spill = Func->makeVariable(IceType_f64); local
3194 Spill->setLinkedTo(Dest);
3195 Spill->setMustNotHaveReg();
3199 Func, Spill, Trait
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/external/v8/src/compiler/
H A Dregister-allocator.cc461 void LiveRange::Spill() { function in class:v8::internal::compiler::LiveRangeBoundArray::LiveRange
1232 // Spill ranges are created for top level, non-splintered ranges. This is so
2588 Spill(range);
2601 Spill(range);
2712 void RegisterAllocator::Spill(LiveRange* range) { function in class:v8::internal::compiler::LiveRangeBoundArray::RegisterAllocator
2720 range->Spill();
2835 Spill(range);
2844 Spill(range);
3170 Spill(current);
3448 Spill(rang
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