Searched defs:SrcVT (Results 1 - 25 of 38) sorted by relevance

12

/external/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp267 EVT SrcVT = Src.getValueType(); local
273 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
275 SrcVT)),
H A DX86ISelDAGToDAG.cpp594 MVT SrcVT = N->getOperand(0).getSimpleValueType(); local
598 if (SrcVT.isVector() || DstVT.isVector())
605 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
626 MemVT = SrcIsSSE ? SrcVT : DstVT;
H A DX86FastISel.cpp97 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
693 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
696 unsigned Src, EVT SrcVT,
698 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1211 EVT SrcVT = TLI.getValueType(DL, RV->getType()); local
1214 if (SrcVT != DstVT) {
1215 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
1223 if (SrcVT
695 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument
2354 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); local
3439 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); local
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp244 EVT SrcVT = Src.getValueType(); local
249 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
250 DAG.getConstant(Offset, SrcVT)),
H A DX86FastISel.cpp86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
308 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
311 unsigned Src, EVT SrcVT,
313 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
754 EVT SrcVT = TLI.getValueType(RV->getType()); local
757 if (SrcVT != DstVT) {
758 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
766 if (SrcVT
310 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument
1275 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); local
1953 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); local
[all...]
H A DX86ISelDAGToDAG.cpp477 EVT SrcVT = N->getOperand(0).getValueType(); local
481 if (SrcVT.isVector() || DstVT.isVector())
486 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
507 MemVT = SrcIsSSE ? SrcVT : DstVT;
/external/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp316 auto SrcVT = TLI->getValueType(DL, Src); local
326 if (DstVT.getSizeInBits() < SrcVT.getSizeInBits())
341 if (DstVT.getSizeInBits() != 64u || SrcVT.getSizeInBits() == 32u)
H A DAArch64ISelDAGToDAG.cpp370 EVT SrcVT; local
372 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
374 SrcVT = N.getOperand(0).getValueType();
376 if (!IsLoadStore && SrcVT == MVT::i8)
378 else if (!IsLoadStore && SrcVT == MVT::i16)
380 else if (SrcVT == MVT::i32)
382 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
387 EVT SrcVT = N.getOperand(0).getValueType(); local
388 if (!IsLoadStore && SrcVT == MVT::i8)
390 else if (!IsLoadStore && SrcVT
[all...]
/external/llvm/lib/Target/X86/Utils/
H A DX86ShuffleDecode.cpp279 void DecodeSubVectorBroadcast(MVT DstVT, MVT SrcVT, argument
281 assert(SrcVT.getScalarType() == DstVT.getScalarType() &&
283 unsigned NumElts = SrcVT.getVectorNumElements();
284 unsigned Scale = DstVT.getSizeInBits() / SrcVT.getSizeInBits();
/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/
H A DCodeGenPrepare.cpp367 EVT SrcVT = TLI.getValueType(CI->getOperand(0)->getType()); local
371 if (SrcVT.isInteger() != DstVT.isInteger())
376 if (SrcVT.bitsLT(DstVT)) return false;
381 if (TLI.getTypeAction(CI->getContext(), SrcVT) ==
383 SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT);
389 if (SrcVT != DstVT)
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp497 EVT SrcVT = LD->getMemoryVT(); local
498 EVT SrcEltVT = SrcVT.getScalarType();
499 unsigned NumElem = SrcVT.getVectorNumElements();
504 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
530 unsigned RemainingBytes = SrcVT.getStoreSize();
794 EVT SrcVT = Src.getValueType(); local
795 int NumSrcElements = SrcVT.getVectorNumElements();
809 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
816 EVT SrcVT local
841 EVT SrcVT = Src.getValueType(); local
[all...]
H A DFastISel.cpp1246 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); local
1249 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1259 if (!TLI.isTypeLegal(SrcVT))
1269 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1296 MVT SrcVT = SrcEVT.getSimpleVT();
1305 if (SrcVT == DstVT) {
1306 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1318 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1653 EVT SrcVT local
[all...]
H A DLegalizeFloatTypes.cpp1410 EVT SrcVT = Src.getValueType(); local
1417 if (SrcVT.bitsLE(MVT::i32)) {
1426 if (SrcVT.bitsLE(MVT::i64)) {
1430 } else if (SrcVT.bitsLE(MVT::i128)) {
1445 SrcVT = Src.getValueType();
1453 switch (SrcVT.getSimpleVT().SimpleTy) {
1472 Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, dl, SrcVT),
H A DSelectionDAGISel.cpp713 EVT SrcVT = Src.getValueType(); local
714 if (!SrcVT.isInteger() || SrcVT.isVector())
H A DLegalizeIntegerTypes.cpp3132 EVT SrcVT = Op.getValueType(); local
3136 // The following optimization is valid only if every value in SrcVT (when
3138 // size of DstVT is >= than the number of bits in SrcVT -1.
3140 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
3141 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
3155 if (SrcVT == MVT::i32)
3157 else if (SrcVT == MVT::i64)
3159 else if (SrcVT == MVT::i128)
3200 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
/external/llvm/lib/Transforms/Scalar/
H A DScalarizer.cpp492 VectorType *SrcVT = dyn_cast<VectorType>(BCI.getSrcTy()); local
493 if (!DstVT || !SrcVT)
497 unsigned SrcNumElems = SrcVT->getNumElements();
529 Type *MidTy = VectorType::get(SrcVT->getElementType(), FanIn);
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp615 EVT SrcVT = TLI.getPointerTy(); local
616 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
624 if (SrcVT.bitsGT(MVT::i32))
625 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
627 else if (SrcVT.bitsLT(MVT::i32))
628 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
665 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); local
668 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
678 if (!TLI.isTypeLegal(SrcVT))
710 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); local
971 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); local
[all...]
H A DLegalizeDAG.cpp1188 EVT SrcVT = LD->getMemoryVT(); local
1189 unsigned SrcWidth = SrcVT.getSizeInBits();
1194 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1202 (SrcVT != MVT::i1 ||
1206 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1211 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1226 Result, DAG.getValueType(SrcVT));
1231 DAG.getValueType(SrcVT));
1237 assert(!SrcVT.isVector() && "Unsupported extload!");
1313 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
[all...]
H A DLegalizeFloatTypes.cpp1171 EVT SrcVT = Src.getValueType(); local
1178 if (SrcVT.bitsLE(MVT::i32)) {
1186 if (SrcVT.bitsLE(MVT::i64)) {
1190 } else if (SrcVT.bitsLE(MVT::i128)) {
1205 SrcVT = Src.getValueType();
1213 switch (SrcVT.getSimpleVT().SimpleTy) {
1230 Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT),
H A DSelectionDAGISel.cpp456 EVT SrcVT = Src.getValueType(); local
457 if (!SrcVT.isInteger() || SrcVT.isVector())
461 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
H A DLegalizeIntegerTypes.cpp2754 EVT SrcVT = Op.getValueType(); local
2758 // The following optimization is valid only if every value in SrcVT (when
2760 // size of DstVT is >= than the number of bits in SrcVT -1.
2762 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 &&
2763 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2777 if (SrcVT == MVT::i32)
2779 else if (SrcVT == MVT::i64)
2781 else if (SrcVT == MVT::i128)
2820 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
/external/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp139 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
140 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
143 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
145 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
146 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
148 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
952 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
955 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
1026 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
1029 if (SrcVT !
1154 MVT SrcVT = ArgVT; local
1162 MVT SrcVT = ArgVT; local
1530 EVT SrcVT, DestVT; local
1575 emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1594 emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1609 emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1618 emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1640 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument
1654 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp164 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
819 MVT SrcVT = SrcEVT.getSimpleVT();
821 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
834 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
835 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
845 switch (SrcVT.SimpleTy) {
885 if (!PPCEmitIntExt(SrcVT, SrcReg
910 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
928 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
954 PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg, bool IsSigned) argument
1109 MVT DstVT, SrcVT; local
1714 PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument
1785 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMFastISel.cpp189 bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
1512 EVT SrcVT, unsigned &ResultReg) {
1513 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1998 EVT SrcVT, DestVT; local
1999 SrcVT = TLI.getValueType(SrcTy, true);
2003 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2022 if (!SrcVT.isSimple())
2024 switch (SrcVT
1511 FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument
[all...]
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp175 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1354 MVT SrcVT = SrcEVT.getSimpleVT();
1368 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1369 SrcVT == MVT::i1) {
1383 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1391 switch (SrcVT.SimpleTy) {
1433 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg
2566 EVT SrcVT, DestVT; local
2584 ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument
[all...]

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