| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/AsmParser/ |
| H A D | MBlazeAsmParser.cpp | 187 void addRegOperands(MCInst &Inst, unsigned N) const { function in struct:__anon22863::MBlazeOperand
|
| /external/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 385 void addRegOperands(MCInst &Inst, unsigned N) const { function in struct:llvm::__anon14393::LanaiOperand
|
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 302 void addRegOperands(MCInst &Inst, unsigned N) const { function in class:__anon14494::SparcOperand
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 385 void addRegOperands(MCInst &Inst, unsigned N) const { function in struct:llvm::X86Operand
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 295 void addRegOperands(MCInst &Inst, unsigned N) const { function in struct:__anon22930::X86Operand
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 551 void addRegOperands(MCInst &Inst, unsigned N) const { function in struct:__anon14460::PPCOperand
552 llvm_unreachable("addRegOperands");
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 268 void addRegOperands(MCInst &Inst, unsigned N) const { function in class:__anon14505::SystemZOperand
|
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 391 void addRegOperands(MCInst &Inst, unsigned N) const { function in class:__anon14213::AMDGPUOperand
397 addRegOperands(Inst, N);
408 addRegOperands(Inst, N);
1668 Op.addRegOperands(Inst, 1);
1693 Op.addRegOperands(Inst, 1);
2137 Op.addRegOperands(Inst, 1);
2180 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
2213 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
2217 ((AMDGPUOperand &)*Operands[I]).addRegOperands(Inst, 1);
2395 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Ins
[all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 352 void addRegOperands(MCInst &Inst, unsigned N) const { function in struct:__anon14302::HexagonOperand
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 963 void addRegOperands(MCInst &Inst, unsigned N) const { function in class:__anon22814::ARMOperand
2806 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2807 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2826 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2827 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2841 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2859 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2871 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2887 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2906 ((ARMOperand*)Operands[2])->addRegOperands(Ins
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1159 void addRegOperands(MCInst &Inst, unsigned N) const { function in class:__anon14183::AArch64Operand
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 810 void addRegOperands(MCInst &Inst, unsigned N) const { function in class:__anon14415::MipsOperand
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 1796 void addRegOperands(MCInst &Inst, unsigned N) const { function in class:__anon14271::ARMOperand
4759 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4768 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
|