Searched defs:imm (Results 51 - 75 of 215) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dintel_batchbuffer.c611 brw_load_register_imm32(struct brw_context *brw, uint32_t reg, uint32_t imm) argument
618 OUT_BATCH(imm);
626 brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm) argument
633 OUT_BATCH(imm & 0xffffffff);
635 OUT_BATCH(imm >> 32);
677 uint32_t offset, uint32_t imm)
691 OUT_BATCH(imm);
700 uint32_t offset, uint64_t imm)
714 OUT_BATCH(imm & 0xffffffffu);
715 OUT_BATCH(imm >> 3
676 brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo, uint32_t offset, uint32_t imm) argument
699 brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo, uint32_t offset, uint64_t imm) argument
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/external/mesa3d/src/mesa/state_tracker/
H A Dst_tgsi_lower_yuv.c37 struct tgsi_full_src_register imm[4]; member in struct:tgsi_yuv_transform
160 ctx->imm[idx].Register.File = TGSI_FILE_IMMEDIATE;
161 ctx->imm[idx].Register.Index = info->immediate_count + idx;
162 ctx->imm[idx].Register.SwizzleX = TGSI_SWIZZLE_X;
163 ctx->imm[idx].Register.SwizzleY = TGSI_SWIZZLE_Y;
164 ctx->imm[idx].Register.SwizzleZ = TGSI_SWIZZLE_Z;
165 ctx->imm[idx].Register.SwizzleW = TGSI_SWIZZLE_W;
259 /* SUB tmpA.xyz, tmpA, imm[3] */
267 reg_src(&inst.Src[1], &ctx->imm[3], SWIZ(X, Y, Z, _));
271 /* DP3 dst.x, tmpA, imm[
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H A Dst_mesa_to_tgsi.c336 struct ureg_src imm; local
361 imm = ureg_imm3f( ureg, 0, 1, -1 );
400 swizzle_4v( imm, mul_swizzle ),
401 swizzle_4v( imm, add_swizzle ) );
407 swizzle_4v( imm, mul_swizzle ) );
412 swizzle_4v( imm, add_swizzle ) );
H A Dst_pbo.c353 struct ureg_src imm; local
369 imm = ureg_DECL_immediate_int(ureg, &zero, 1);
381 ureg_EMIT(ureg, ureg_scalar(imm, TGSI_SWIZZLE_X));
/external/pcre/dist2/src/sljit/
H A DsljitNativeX86_64.c29 static sljit_s32 emit_load_imm64(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) argument
38 sljit_unaligned_store_sw(inst, imm);
331 static sljit_s32 emit_do_imm32(struct sljit_compiler *compiler, sljit_u8 rex, sljit_u8 opcode, sljit_sw imm) argument
342 sljit_unaligned_store_s32(inst, imm);
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
H A DPTXISelDAGToDAG.cpp57 bool SelectImm(const SDValue &operand, SDValue &imm);
211 // Match memory operand of the form [reg], [imm+reg], and [reg+imm]
256 // let SelectADDRii handle the [imm] case
271 // let SelectADDRii handle the [imm+imm] case
275 // try [reg+imm] and [imm+reg]
282 // neither [reg+imm] nor [imm
341 SelectImm(const SDValue &operand, SDValue &imm) argument
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/external/v8/src/arm64/
H A Dinstructions-arm64.cc241 Instr imm; local
243 imm = Assembler::ImmPCRelAddress(static_cast<int>(target_offset));
244 SetInstructionBits(Mask(~ImmPCRel_mask) | imm);
307 Instr imm = Assembler::ImmLLiteral( local
311 SetInstructionBits(Mask(~mask) | imm);
/external/v8/src/
H A Dmacro-assembler.h225 explicit ParameterCount(int imm) : reg_(no_reg), immediate_(imm) {} argument
/external/vixl/src/aarch32/
H A Dinstructions-aarch32.cc605 ImmediateT32::ImmediateT32(uint32_t imm) { argument
607 if ((imm & ~0xff) == 0) {
608 SetEncodingValue(imm);
611 if ((imm >> 16) == (imm & 0xffff)) {
612 if ((imm & 0xff00) == 0) {
614 SetEncodingValue((imm & 0xff) | (0x1 << 8));
617 if ((imm & 0xff) == 0) {
619 SetEncodingValue(((imm >> 8) & 0xff) | (0x2 << 8));
622 if (((imm >>
645 IsImmediateT32(uint32_t imm) argument
679 ImmediateA32(uint32_t imm) argument
695 IsImmediateA32(uint32_t imm) argument
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/external/capstone/arch/Mips/
H A DMipsInstPrinter.c206 int64_t imm = MCOperand_getImm(Op); local
208 if (imm) { // only print Imm offset if it is not 0
209 if (imm >= 0) {
210 if (imm > HEX_THRESHOLD)
211 SStream_concat(O, "0x%"PRIx64, imm);
213 SStream_concat(O, "%"PRIu64, imm);
215 if (imm < -HEX_THRESHOLD)
216 SStream_concat(O, "-0x%"PRIx64, -imm);
218 SStream_concat(O, "-%"PRIu64, -imm);
222 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
249 int64_t imm = MCOperand_getImm(MO); local
274 uint8_t imm = (uint8_t)MCOperand_getImm(MO); local
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/external/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp200 MCOperand imm = MCOperand::createExpr(MCConstantExpr::create(12, local
202 EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
212 MCOperand imm = MCOperand::createExpr(MCConstantExpr::create(32, local
214 EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_aos.c1010 float imm[4]; local
1014 imm[chan] = 0.0f;
1018 imm[swizzle] = parse.FullToken.FullImmediate.u[chan].Float;
1022 imm[0], imm[1], imm[2], imm[3],
/external/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_point_sprite.c155 struct tgsi_full_immediate *imm)
159 ctx->emit_immediate(ctx, imm);
154 psprite_immediate(struct tgsi_transform_context *ctx, struct tgsi_full_immediate *imm) argument
/external/mesa3d/src/gallium/auxiliary/util/
H A Du_simple_shaders.c258 struct ureg_src imm = ureg_imm4f( ureg, 0, 0, 0, 1 ); local
260 ureg_MOV( ureg, out, imm );
325 struct ureg_src imm; local
351 imm = ureg_imm4f( ureg, 0, 0, 0, 1 );
353 ureg_MOV( ureg, out, imm );
377 struct ureg_src imm; local
412 imm = ureg_imm4f( ureg, 0, 0, 0, 1 );
414 ureg_MOV( ureg, out, imm );
441 struct ureg_src imm; local
467 imm
898 struct ureg_src imm; local
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/external/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_translate.c1121 const struct tgsi_full_immediate *imm local
1125 assert( imm->Immediate.NrTokens <= 4 + 1 );
1126 for (j = 0; j < imm->Immediate.NrTokens - 1; j++) {
1127 p->immediates[pos][j] = imm->u[j].Float;
/external/mesa3d/src/mesa/drivers/dri/nouveau/
H A Dnouveau_vbo_t.c59 GLboolean imm = (render->mode == IMM); local
72 imm ? array->BufferObj : NULL,
73 array->Ptr, imm, ctx);
/external/v8/src/compiler/
H A Dregister-allocator-verifier.cc154 const ImmediateOperand* imm = ImmediateOperand::cast(op); local
155 int value = imm->type() == ImmediateOperand::INLINE ? imm->inline_value()
156 : imm->indexed_value();
220 const ImmediateOperand* imm = ImmediateOperand::cast(op); local
221 int value = imm->type() == ImmediateOperand::INLINE
222 ? imm->inline_value()
223 : imm->indexed_value();
/external/v8/src/mips/
H A Dassembler-mips-inl.h165 int32_t imm = reinterpret_cast<int32_t>(target); local
166 DCHECK((imm & 3) == 0);
170 Assembler::UnpackTargetAddressUnsigned(imm, lui_offset_u, jic_offset_u);
179 instr1 | ((imm >> kLuiShift) & kImm16Mask));
181 instr2 | (imm & kImm16Mask));
252 int32_t imm = (instr1 & static_cast<int32_t>(kImm16Mask)) << kLuiShift; local
253 imm |= (instr2 & static_cast<int32_t>(kImm16Mask));
254 return reinterpret_cast<Address>(imm);
/external/vixl/src/aarch64/
H A Dinstructions-aarch64.cc347 Instr imm = Assembler::ImmPCRelAddress(static_cast<int32_t>(imm21)); local
349 SetInstructionBits(Mask(~ImmPCRel_mask) | imm);
389 Instr imm = Assembler::ImmLLiteral(static_cast<int>(offset)); local
392 SetInstructionBits(Mask(~mask) | imm);
/external/capstone/arch/PowerPC/
H A DPPCInstPrinter.c119 ppc->operands[ppc->op_count].imm = SH;
364 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
381 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
405 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
421 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
437 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
460 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
489 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
508 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
529 int imm; local
677 int32_t imm = (int32_t)MCOperand_getImm(Op); local
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/external/llvm/lib/Target/Mips/
H A DMips16ISelLowering.cpp739 int64_t imm = MI.getOperand(1).getImm(); local
742 if (isUInt<8>(imm))
744 else if ((!ImmSigned && isUInt<16>(imm)) ||
745 (ImmSigned && isInt<16>(imm)))
749 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
/external/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_disasm.c118 int imm; member in struct:opc_operands
450 printf("label_%04d", operands->imm);
575 int imm = (instr->dword3 & VIV_ISA_WORD_3_SRC2_IMM__MASK) local
584 .imm = imm,
/external/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dfd2_compiler.c210 struct tgsi_full_immediate *imm = local
213 memcpy(ctx->so->immediates[n].val, imm->u, 16);
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_build_util.cpp52 BuildUtil::addImmediate(ImmediateValue *imm) argument
57 unsigned int pos = u32Hash(imm->reg.data.u32);
61 imms[pos] = imm;
364 ImmediateValue *imm = imms[pos]; local
365 if (!imm) {
366 imm = new_ImmediateValue(prog, u);
367 addImmediate(imm);
369 return imm;
375 ImmediateValue *imm = new_ImmediateValue(prog, (uint32_t)0); local
377 imm
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H A Dnv50_ir_from_tgsi.cpp1175 void Source::scanImmediate(const struct tgsi_full_immediate *imm) argument
1182 info->immd.data[n * 4 + c] = imm->u[c].Uint;
1184 info->immd.type[n] = imm->Immediate.DataType;

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