Searched defs:indirect_offset (Results 1 - 11 of 11) sorted by relevance

/external/mesa3d/src/mesa/state_tracker/
H A Dst_cb_compute.c41 GLintptr indirect_offset)
66 info.indirect_offset = indirect_offset;
79 GLintptr indirect_offset)
84 st_dispatch_compute_common(ctx, NULL, NULL, indirect, indirect_offset);
37 st_dispatch_compute_common(struct gl_context *ctx, const GLuint *num_groups, const GLuint *group_size, struct pipe_resource *indirect, GLintptr indirect_offset) argument
78 st_dispatch_compute_indirect(struct gl_context *ctx, GLintptr indirect_offset) argument
H A Dst_draw.c289 GLsizeiptr indirect_offset,
333 info.indirect_offset = indirect_offset;
350 info.indirect_offset += stride;
286 st_indirect_draw_vbo(struct gl_context *ctx, GLuint mode, struct gl_buffer_object *indirect_data, GLsizeiptr indirect_offset, unsigned draw_count, unsigned stride, struct gl_buffer_object *indirect_params, GLsizeiptr indirect_params_offset, const struct _mesa_index_buffer *ib) argument
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_compute.c40 GLintptr indirect_offset = brw->compute.num_work_groups_offset; local
45 indirect_offset + 0);
48 indirect_offset + 4);
51 indirect_offset + 8);
70 indirect_offset + 0);
83 indirect_offset + 4);
96 indirect_offset + 8);
H A Dbrw_vec4_tcs.cpp171 const src_reg &indirect_offset)
180 indirect_offset);
193 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
206 const src_reg &indirect_offset)
213 brw_imm_ud(dst.writemask << first_component), indirect_offset);
233 const src_reg &indirect_offset)
242 brw_imm_ud(writemask), indirect_offset);
271 src_reg indirect_offset = get_indirect_offset(instr); local
291 first_component, indirect_offset);
294 imm_offset + 1, 0, indirect_offset); local
167 emit_input_urb_read(const dst_reg &dst, const src_reg &vertex_index, unsigned base_offset, unsigned first_component, const src_reg &indirect_offset) argument
203 emit_output_urb_read(const dst_reg &dst, unsigned base_offset, unsigned first_component, const src_reg &indirect_offset) argument
230 emit_urb_write(const src_reg &value, unsigned writemask, unsigned base_offset, const src_reg &indirect_offset) argument
317 src_reg indirect_offset = get_indirect_offset(instr); local
333 src_reg indirect_offset = get_indirect_offset(instr); local
370 imm_offset, indirect_offset); local
[all...]
H A Dbrw_vec4_tes.cpp198 src_reg indirect_offset = get_indirect_offset(instr); local
206 if (indirect_offset.file != BAD_FILE) {
209 input_read_header, indirect_offset);
H A Dbrw_reg.h263 int indirect_offset:10; /* relative addressing offset */ member in struct:brw_reg::__anon17115::__anon17116
393 reg.indirect_offset = 0;
1021 reg.indirect_offset = offset;
1031 reg.indirect_offset = offset;
1042 reg.indirect_offset = offset;
/external/mesa3d/src/mesa/vbo/
H A Dvbo.h63 GLsizeiptr indirect_offset; member in struct:_mesa_prim
117 GLsizeiptr indirect_offset,
H A Dvbo_context.c140 GLsizeiptr indirect_offset,
162 for (i = 0; i < draw_count; ++i, indirect_offset += stride) {
165 prim[i].indirect_offset = indirect_offset;
137 vbo_draw_indirect_prims(struct gl_context *ctx, GLuint mode, struct gl_buffer_object *indirect_data, GLsizeiptr indirect_offset, unsigned draw_count, unsigned stride, struct gl_buffer_object *indirect_params, GLsizeiptr indirect_params_offset, const struct _mesa_index_buffer *ib) argument
/external/mesa3d/src/amd/common/
H A Dac_nir_to_llvm.h64 uint32_t indirect_offset; member in struct:ac_userdata_info
/external/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_program.c88 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0); local
113 indirect_offset = qir_ADD(c, indirect_offset,
118 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
119 indirect_offset = qir_MIN_NOIMM(c, indirect_offset,
124 indirect_offset,
/external/mesa3d/src/gallium/include/pipe/
H A Dp_state.h700 unsigned indirect_offset; /**< must be 4 byte aligned */ member in struct:pipe_draw_info
787 unsigned indirect_offset; /**< must be 4 byte aligned */ member in struct:pipe_grid_info

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