/external/v8/src/compiler/ |
H A D | instruction-scheduler.cc | 64 Instruction* instr) 65 : instr_(instr), 68 latency_(GetInstructionLatency(instr)), 120 void InstructionScheduler::AddInstruction(Instruction* instr) { argument 121 ScheduleGraphNode* new_node = new (zone()) ScheduleGraphNode(zone(), instr); 123 if (IsBlockTerminator(instr)) { 129 } else if (IsFixedRegisterParameter(instr)) { 141 if ((last_deopt_ != nullptr) && DependsOnDeoptimization(instr)) { 147 if (HasSideEffect(instr)) { 156 } else if (IsLoadOperation(instr)) { 62 ScheduleGraphNode( Zone* zone, Instruction* instr) argument [all...] |
H A D | jump-threading.cc | 79 Instruction* instr = code->InstructionAt(i); local 80 if (!instr->AreMovesRedundant()) { 84 } else if (FlagsModeField::decode(instr->opcode()) != kFlags_none) { 88 } else if (instr->IsNop()) { 92 } else if (instr->arch_opcode() == kArchJmp) { 103 fw = code->InputRpo(instr, 0); 158 Instruction* instr = code->InstructionAt(i); local 159 if (FlagsModeField::decode(instr->opcode()) == kFlags_branch) { 161 } else if (instr->arch_opcode() == kArchJmp) { 165 instr [all...] |
/external/v8/src/crankshaft/ |
H A D | hydrogen-range-analysis.cc | 64 HChange* instr = HChange::cast(value); local 67 Representation from = instr->value()->representation(); 68 DCHECK(from.Equals(instr->from())); 70 DCHECK(instr->to().IsTagged() || 71 instr->to().IsDouble() || 72 instr->to().IsSmiOrInteger32()); 73 PropagateMinusZeroChecks(instr->value()); 109 HInstruction* instr = it.Current(); local 110 if (instr->HasRange()) instr 225 HUnaryMathOperation* instr = HUnaryMathOperation::cast(value); local 239 HChange* instr = HChange::cast(value); local 247 HForceRepresentation* instr = HForceRepresentation::cast(value); local 250 HMod* instr = HMod::cast(value); local 256 HBinaryOperation* instr = HBinaryOperation::cast(value); local 263 HMathFloorOfDiv* instr = HMathFloorOfDiv::cast(value); local 266 HBinaryOperation* instr = HBinaryOperation::cast(value); local 273 HMathMinMax* instr = HMathMinMax::cast(value); local [all...] |
H A D | hydrogen-removable-simulates.cc | 19 State* Process(HInstruction* instr, Zone* zone) { argument 23 reinterpret_cast<void*>(this), instr->block()->block_id(), 24 instr->id(), instr->Mnemonic()); 29 if (instr->IsSimulate()) { 30 HSimulate* current_simulate = HSimulate::cast(instr); 42 DCHECK(!(instr->IsEnterInlined() && 43 HSimulate::cast(instr->previous())->is_candidate_for_removal())); 44 if (instr->IsLeaveInlined() || instr 177 Process(HInstruction* instr, Zone* zone) argument [all...] |
/external/valgrind/callgrind/ |
H A D | callstack.c | 239 UInt instr = from->bb->jmp[jmp].instr; local 241 from->bb->instr[instr].instr_offset + 242 from->bb->instr[instr].instr_size;
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/external/vixl/src/aarch32/ |
H A D | location-aarch32.cc | 55 static bool Is16BitEncoding(uint16_t instr) { argument 56 return instr < (kLowestT32_32Opcode >> 16); 68 uint32_t instr = static_cast<uint32_t>(instr_ptr[0]); local 69 instr = encoder->Encode(instr, from, this); 71 VIXL_ASSERT((instr & ~0xffff) == 0); 72 instr_ptr[0] = static_cast<uint16_t>(instr); 74 uint32_t instr = local 76 instr = encoder->Encode(instr, fro [all...] |
/external/capstone/arch/PowerPC/ |
H A D | PPCDisassembler.c | 369 MCInst *instr, uint16_t *size, uint64_t address, void *info) 371 DecodeStatus status = getInstruction(instr, 368 PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info) argument
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/external/capstone/arch/X86/ |
H A D | X86Disassembler.c | 787 MCInst *instr, uint16_t *size, uint64_t address, void *_info) 801 if (instr->flat_insn->detail) { 802 instr->flat_insn->detail->x86.op_count = 0; 803 instr->flat_insn->detail->x86.sse_cc = X86_SSE_CC_INVALID; 804 instr->flat_insn->detail->x86.avx_cc = X86_AVX_CC_INVALID; 805 instr->flat_insn->detail->x86.avx_sae = false; 806 instr->flat_insn->detail->x86.avx_rm = X86_AVX_RM_INVALID; 808 memset(instr->flat_insn->detail->x86.prefix, 0, sizeof(instr->flat_insn->detail->x86.prefix)); 809 memset(instr 786 X86_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *_info) argument [all...] |
/external/emma/core/java12/com/vladium/emma/instr/ |
H A D | InstrProcessor.java | 9 package com.vladium.emma.instr; 37 public static final String PROPERTY_EXCLUDE_SYNTHETIC_METHODS = "instr.exclude_synthetic_methods"; 38 public static final String PROPERTY_EXCLUDE_BRIDGE_METHODS = "instr.exclude_bridge_methods"; 39 public static final String PROPERTY_DO_SUID_COMPENSATION = "instr.do_suid_compensation"; 167 // with the instr path:
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/external/jacoco/org.jacoco.core/src/org/jacoco/core/internal/instr/ |
H A D | DuplicateFrameEliminator.java | 12 package org.jacoco.core.internal.instr;
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/external/jacoco/org.jacoco.core.test/src/org/jacoco/core/internal/instr/ |
H A D | ProbeArrayStrategyFactoryTest.java | 12 package org.jacoco.core.internal.instr;
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/external/mesa3d/src/compiler/nir/ |
H A D | nir_instr_set.c | 51 hash_alu(uint32_t hash, const nir_alu_instr *instr) argument 53 hash = HASH(hash, instr->op); 54 hash = HASH(hash, instr->dest.dest.ssa.num_components); 55 hash = HASH(hash, instr->dest.dest.ssa.bit_size); 56 /* We explicitly don't hash instr->dest.dest.exact */ 58 if (nir_op_infos[instr->op].algebraic_properties & NIR_OP_IS_COMMUTATIVE) { 59 assert(nir_op_infos[instr->op].num_inputs == 2); 60 uint32_t hash0 = hash_alu_src(hash, &instr->src[0], 61 nir_ssa_alu_instr_src_components(instr, 0)); 62 uint32_t hash1 = hash_alu_src(hash, &instr 82 hash_load_const(uint32_t hash, const nir_load_const_instr *instr) argument 101 hash_phi(uint32_t hash, const nir_phi_instr *instr) argument 124 hash_intrinsic(uint32_t hash, const nir_intrinsic_instr *instr) argument 143 hash_tex(uint32_t hash, const nir_tex_instr *instr) argument 178 const nir_instr *instr = data; local 424 instr_can_rewrite(nir_instr *instr) argument 465 nir_instr_get_dest_ssa_def(nir_instr *instr) argument 506 nir_instr_set_add_or_rewrite(struct set *instr_set, nir_instr *instr) argument 534 nir_instr_set_remove(struct set *instr_set, nir_instr *instr) argument [all...] |
H A D | nir_lower_double_ops.c | 460 lower_doubles_instr(nir_alu_instr *instr, nir_lower_doubles_options options) argument 462 assert(instr->dest.dest.is_ssa); 463 if (instr->dest.dest.ssa.bit_size != 64) 466 switch (instr->op) { 517 nir_builder_init(&bld, nir_cf_node_get_function(&instr->instr.block->cf_node)); 518 bld.cursor = nir_before_instr(&instr->instr); 520 nir_ssa_def *src = nir_fmov_alu(&bld, instr->src[0], 521 instr [all...] |
H A D | nir_lower_io.c | 339 nir_ssa_dest_init(&bary_setup->instr, &bary_setup->dest, 2, 32, NULL); 345 nir_builder_instr_insert(&state->builder, &bary_setup->instr); 368 nir_foreach_instr_safe(instr, block) { 369 if (instr->type != nir_instr_type_intrinsic) 372 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); 412 b->cursor = nir_before_instr(instr); 465 nir_ssa_dest_init(&replacement->instr, &replacement->dest, 471 nir_dest_copy(&replacement->dest, &intrin->dest, &intrin->instr); 475 nir_instr_insert_before(&intrin->instr, &replacement->instr); 519 nir_get_io_offset_src(nir_intrinsic_instr *instr) argument 545 nir_get_io_vertex_index_src(nir_intrinsic_instr *instr) argument [all...] |
H A D | nir_opt_gcm.c | 51 /* Flags used in the instr->pass_flags field for various instruction states */ 61 nir_instr *instr; member in struct:gcm_state 104 * This function also serves to initialize the instr->pass_flags field. 111 nir_foreach_instr_safe(instr, block) { 112 switch (instr->type) { 114 switch (nir_instr_as_alu(instr)->op) { 122 instr->pass_flags = GCM_INSTR_PINNED; 126 instr->pass_flags = 0; 132 switch (nir_instr_as_tex(instr)->op) { 137 instr 207 nir_instr *instr = state->instr; local 241 gcm_schedule_early_instr(nir_instr *instr, struct gcm_state *state) argument 356 gcm_schedule_late_instr(nir_instr *instr, struct gcm_state *state) argument 401 gcm_place_instr(nir_instr *instr, struct gcm_state *state) argument 494 nir_instr *instr = exec_node_data(nir_instr, local [all...] |
H A D | nir_search.c | 39 match_expression(const nir_search_expression *expr, nir_alu_instr *instr, 95 match_value(const nir_search_value *value, nir_alu_instr *instr, unsigned src, argument 108 if (!instr->src[src].src.is_ssa) 114 if (nir_op_infos[instr->op].input_sizes[src] != 0) { 115 num_components = nir_op_infos[instr->op].input_sizes[src]; 120 new_swizzle[i] = instr->src[src].swizzle[swizzle[i]]; 124 nir_src_bit_size(instr->src[src].src) != value->bit_size) 129 if (instr->src[src].src.ssa->parent_instr->type != nir_instr_type_alu) 133 nir_instr_as_alu(instr->src[src].src.ssa->parent_instr), 141 if (state->variables[var->variable].src.ssa != instr 246 match_expression(const nir_search_expression *expr, nir_alu_instr *instr, unsigned num_components, const uint8_t *swizzle, struct match_state *state) argument 439 construct_value(const nir_search_value *value, unsigned num_components, bitsize_tree *bitsize, struct match_state *state, nir_instr *instr, void *mem_ctx) argument 571 nir_replace_instr(nir_alu_instr *instr, const nir_search_expression *search, const nir_search_value *replace, void *mem_ctx) argument [all...] |
/external/mesa3d/src/gallium/auxiliary/gallivm/ |
H A D | lp_bld_tgsi.c | 519 const struct tgsi_full_instruction *instr = local 522 tgsi_get_opcode_info(instr->Instruction.Opcode); 523 if (!lp_build_tgsi_inst_llvm(bld_base, instr)) {
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/external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
H A D | fd2_program.c | 174 struct ir2_instruction *instr = so->vfetch_instrs[i]; local 189 instr->fetch.const_idx = 20 + (i / 3); 190 instr->fetch.const_idx_sel = i % 3; 192 instr->fetch.fmt = fd2_pipe2surface(format); 193 instr->fetch.is_normalized = desc->channel[j].normalized; 194 instr->fetch.is_signed = 196 instr->fetch.stride = vb->stride ? : 1; 197 instr->fetch.offset = elem->src_offset; 200 instr->regs[0]->swizzle[j] = "xyzw01__"[desc->swizzle[j]]; 202 assert(instr 228 struct ir2_instruction *instr = so->tfetch_instrs[i].instr; local 307 struct ir2_instruction *instr; local 349 struct ir2_instruction *instr; local 397 struct ir2_instruction *instr; local 430 struct ir2_instruction *instr; local [all...] |
H A D | ir-a2xx.c | 32 #include "instr-a2xx.h" 40 static int cf_emit(struct ir2_cf *cf, instr_cf_t *instr); 42 static int instr_emit(struct ir2_instruction *instr, uint32_t *dwords, 105 struct ir2_instruction *instr = cf->exec.instrs[j]; local 107 if (instr->instr_type == IR2_FETCH) 109 if (instr->sync) 208 static int cf_emit(struct ir2_cf *cf, instr_cf_t *instr) argument 210 memset(instr, 0, sizeof(*instr)); 212 instr 261 struct ir2_instruction *instr = local 277 instr_emit_fetch(struct ir2_instruction *instr, uint32_t *dwords, uint32_t idx, struct ir2_shader_info *info) argument 362 instr_emit_alu(struct ir2_instruction *instr, uint32_t *dwords, struct ir2_shader_info *info) argument 480 instr_emit(struct ir2_instruction *instr, uint32_t *dwords, uint32_t idx, struct ir2_shader_info *info) argument 491 ir2_reg_create(struct ir2_instruction *instr, int num, const char *swizzle, int flags) argument [all...] |
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
H A D | disasm-a3xx.c | 33 #include "instr-a3xx.h" 151 static void print_instr_cat0(instr_t *instr) argument 153 instr_cat0_t *cat0 = &instr->cat0; 174 static void print_instr_cat1(instr_t *instr) argument 176 instr_cat1_t *cat1 = &instr->cat1; 233 static void print_instr_cat2(instr_t *instr) argument 235 instr_cat2_t *cat2 = &instr->cat2; 313 static void print_instr_cat3(instr_t *instr) argument 315 instr_cat3_t *cat3 = &instr->cat3; 354 static void print_instr_cat4(instr_t *instr) argument 380 print_instr_cat5(instr_t *instr) argument 479 print_instr_cat6(instr_t *instr) argument 823 ir3_instr_name(struct ir3_instruction *instr) argument 831 instr_t *instr = (instr_t *)dwords; local [all...] |
/external/mesa3d/src/gallium/drivers/vc4/ |
H A D | vc4_nir_lower_io.c | 52 nir_instr_remove(&intr->instr); 174 b->cursor = nir_before_instr(&intr->instr); 199 nir_ssa_dest_init(&intr_comp->instr, &intr_comp->dest, 1, 32, NULL); 200 nir_builder_instr_insert(b, &intr_comp->instr); 244 b->cursor = nir_after_instr(&intr->instr); 316 nir_instr_remove(&intr->instr); 325 b->cursor = nir_before_instr(&intr->instr); 333 nir_ssa_dest_init(&intr_comp->instr, &intr_comp->dest, 1, 32, NULL); 349 nir_builder_instr_insert(b, &intr_comp->instr); 357 struct nir_instr *instr) 356 vc4_nir_lower_io_instr(struct vc4_compile *c, nir_builder *b, struct nir_instr *instr) argument [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_vec4_tcs.cpp | 52 vec4_tcs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr) argument 255 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) argument 257 switch (instr->intrinsic) { 259 emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD), 264 get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD)); 267 emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D), 271 src_reg indirect_offset = get_indirect_offset(instr); 272 unsigned imm_offset = instr->const_index[0]; 274 nir_const_value *vertex_const = nir_src_as_const_value(instr->src[0]); 277 : get_nir_src(instr [all...] |
H A D | brw_vec4_tes.cpp | 55 vec4_tes_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr) argument 57 switch (instr->intrinsic) { 62 vec4_visitor::nir_setup_system_value_intrinsic(instr); 159 vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) argument 164 switch (instr->intrinsic) { 167 emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F), 172 emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F), 176 emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F), 183 emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F), 187 emit(MOV(get_nir_dest(instr [all...] |
/external/minijail/ |
H A D | bpf.c | 207 struct sock_filter *instr; local 219 instr = &filter[offset]; 220 if (instr->code != (BPF_JMP + BPF_JA)) 222 switch ((instr->jt << 8) | instr->jf) { 224 if (instr->k >= labels->count) { 225 warn("nonexistent label id: %u", instr->k); 228 if (labels->labels[instr->k].location == 0xffffffff) { 230 labels->labels[instr->k].label); 233 instr [all...] |
H A D | bpf.h | 128 static inline size_t set_bpf_instr(struct sock_filter *instr, argument 132 instr->code = code; 133 instr->k = k; 134 instr->jt = jt; 135 instr->jf = jf;
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