Searched defs:qreg (Results 1 - 4 of 4) sorted by relevance
| /external/vixl/test/aarch64/ |
| H A D | test-utils-aarch64.h | 116 inline vec128_t qreg(unsigned code) const { return dump_.q_[code]; } function in class:vixl::aarch64::RegisterDump
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| /external/vixl/test/aarch32/ |
| H A D | test-utils-aarch32.cc | 168 const QRegister& qreg) {
170 vec128_t result = core->GetQRegisterBits(qreg.GetCode());
165 Equal128(uint64_t expected_h, uint64_t expected_l, const RegisterDump* core, const QRegister& qreg) argument
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| /external/mesa3d/src/gallium/drivers/vc4/ |
| H A D | vc4_qir.h | 91 struct qreg { struct
97 static inline struct qreg qir_reg(enum qfile file, uint32_t index)
99 return (struct qreg){file, index};
200 struct qreg dst;
201 struct qreg src[3];
421 * qreg for the values.
434 struct qreg *inputs;
435 struct qreg *outputs;
437 struct qreg color_reads[VC4_MAX_SAMPLES];
438 struct qreg sample_color
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| /external/v8/src/arm/ |
| H A D | simulator-arm.cc | 903 void Simulator::get_q_register(int qreg, T* value) { argument
904 DCHECK((qreg >= 0) && (qreg < num_q_registers));
905 memcpy(value, vfp_registers_ + qreg * 4, kSimd128Size);
909 void Simulator::set_q_register(int qreg, const T* value) { argument
910 DCHECK((qreg >= 0) && (qreg < num_q_registers));
911 memcpy(vfp_registers_ + qreg * 4, value, kSimd128Size);
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