/art/runtime/interpreter/ |
H A D | shadow_frame.cc | 32 uint16_t reg = accessor.RegistersSize() - accessor.InsSize(); local 33 return GetVRegReference(reg);
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/art/test/404-optimizing-allocator/src/ |
H A D | Main.java | 17 // Note that $opt$reg$ is a marker for the optimizing compiler to test 23 expectEquals(4, $opt$reg$TestLostCopy()); 24 expectEquals(-10, $opt$reg$TestTwoLive()); 25 expectEquals(-20, $opt$reg$TestThreeLive()); 26 expectEquals(5, $opt$reg$TestFourLive()); 27 expectEquals(10, $opt$reg$TestMultipleLive()); 28 expectEquals(1, $opt$reg$TestWithBreakAndContinue()); 29 expectEquals(-15, $opt$reg$testSpillInIf(5, 6, 7)); 30 expectEquals(-567, $opt$reg$TestAgressiveLive1(1, 2, 3, 4, 5, 6, 7)); 31 expectEquals(-77, $opt$reg [all...] |
/art/compiler/utils/mips64/ |
H A D | managed_register_mips64.cc | 51 std::ostream& operator<<(std::ostream& os, const Mips64ManagedRegister& reg) { argument 52 reg.Print(os);
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H A D | managed_register_mips64_test.cc | 25 Mips64ManagedRegister reg = ManagedRegister::NoRegister().AsMips64(); local 26 EXPECT_TRUE(reg.IsNoRegister()); 27 EXPECT_FALSE(reg.Overlaps(reg)); 31 Mips64ManagedRegister reg = Mips64ManagedRegister::FromGpuRegister(ZERO); local 32 EXPECT_FALSE(reg.IsNoRegister()); 33 EXPECT_TRUE(reg.IsGpuRegister()); 34 EXPECT_FALSE(reg.IsFpuRegister()); 35 EXPECT_FALSE(reg.IsVectorRegister()); 36 EXPECT_EQ(ZERO, reg 110 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0); local 156 Mips64ManagedRegister reg = Mips64ManagedRegister::FromVectorRegister(W0); local 278 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0); local [all...] |
/art/compiler/utils/x86/ |
H A D | managed_register_x86_test.cc | 26 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); local 27 EXPECT_TRUE(reg.IsNoRegister()); 28 EXPECT_TRUE(!reg.Overlaps(reg)); 32 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); local 33 EXPECT_TRUE(!reg.IsNoRegister()); 34 EXPECT_TRUE(reg.IsCpuRegister()); 35 EXPECT_TRUE(!reg.IsXmmRegister()); 36 EXPECT_TRUE(!reg.IsX87Register()); 37 EXPECT_TRUE(!reg 66 X86ManagedRegister reg = X86ManagedRegister::FromXmmRegister(XMM0); local 92 X86ManagedRegister reg = X86ManagedRegister::FromX87Register(ST0); local 118 X86ManagedRegister reg = X86ManagedRegister::FromRegisterPair(EAX_EDX); local 256 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); local [all...] |
H A D | managed_register_x86.cc | 41 RegisterPair reg; // Used to verify that the enum is in sync. member in struct:art::x86::RegisterPairDescriptor 53 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { argument 54 if (reg == kNoRegisterPair) { 57 os << X86ManagedRegister::FromRegisterPair(reg); 84 CHECK_EQ(r, kRegisterPairs[r].reg); 93 CHECK_EQ(r, kRegisterPairs[r].reg); 114 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg) { argument 115 reg.Print(os);
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/art/compiler/utils/x86_64/ |
H A D | managed_register_x86_64_test.cc | 25 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); local 26 EXPECT_TRUE(reg.IsNoRegister()); 27 EXPECT_TRUE(!reg.Overlaps(reg)); 31 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); local 32 EXPECT_TRUE(!reg.IsNoRegister()); 33 EXPECT_TRUE(reg.IsCpuRegister()); 34 EXPECT_TRUE(!reg.IsXmmRegister()); 35 EXPECT_TRUE(!reg.IsX87Register()); 36 EXPECT_TRUE(!reg 65 X86_64ManagedRegister reg = X86_64ManagedRegister::FromXmmRegister(XMM0); local 91 X86_64ManagedRegister reg = X86_64ManagedRegister::FromX87Register(ST0); local 117 X86_64ManagedRegister reg = X86_64ManagedRegister::FromRegisterPair(EAX_EDX); local 255 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); local [all...] |
H A D | managed_register_x86_64.cc | 40 RegisterPair reg; // Used to verify that the enum is in sync. member in struct:art::x86_64::RegisterPairDescriptor 52 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { argument 53 os << X86_64ManagedRegister::FromRegisterPair(reg); 79 CHECK_EQ(r, kRegisterPairs[r].reg); 88 CHECK_EQ(r, kRegisterPairs[r].reg); 109 std::ostream& operator<<(std::ostream& os, const X86_64ManagedRegister& reg) { argument 110 reg.Print(os);
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/art/compiler/utils/arm/ |
H A D | managed_register_arm.cc | 92 std::ostream& operator<<(std::ostream& os, const ArmManagedRegister& reg) { argument 93 reg.Print(os);
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H A D | managed_register_arm_test.cc | 25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); local 26 EXPECT_TRUE(reg.IsNoRegister()); 27 EXPECT_TRUE(!reg.Overlaps(reg)); 31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); local 32 EXPECT_TRUE(!reg.IsNoRegister()); 33 EXPECT_TRUE(reg.IsCoreRegister()); 34 EXPECT_TRUE(!reg.IsSRegister()); 35 EXPECT_TRUE(!reg.IsDRegister()); 36 EXPECT_TRUE(!reg 69 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); local 126 ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0); local 227 ArmManagedRegister reg = ArmManagedRegister::FromRegisterPair(R0_R1); local 459 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); local [all...] |
/art/compiler/utils/arm64/ |
H A D | managed_register_arm64.cc | 102 std::ostream& operator<<(std::ostream& os, const Arm64ManagedRegister& reg) { argument 103 reg.Print(os);
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H A D | managed_register_arm64_test.cc | 27 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); local 28 EXPECT_TRUE(reg.IsNoRegister()); 29 EXPECT_TRUE(!reg.Overlaps(reg)); 34 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); local 36 EXPECT_TRUE(!reg.IsNoRegister()); 37 EXPECT_TRUE(reg.IsXRegister()); 38 EXPECT_TRUE(!reg.IsWRegister()); 39 EXPECT_TRUE(!reg.IsDRegister()); 40 EXPECT_TRUE(!reg 107 Arm64ManagedRegister reg = Arm64ManagedRegister::FromWRegister(W0); local 169 Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0); local 220 Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); local 376 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); local [all...] |
/art/compiler/utils/mips/ |
H A D | managed_register_mips.cc | 92 std::ostream& operator<<(std::ostream& os, const MipsManagedRegister& reg) { argument 93 reg.Print(os); 97 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { argument 98 os << MipsManagedRegister::FromRegisterPair(reg);
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/art/runtime/arch/arm64/ |
H A D | context_arm64.cc | 61 void Arm64Context::SetGPR(uint32_t reg, uintptr_t value) { argument 62 DCHECK_LT(reg, arraysize(gprs_)); 63 // Note: we use kPC == XZR, so do not ensure that reg != XZR. 64 DCHECK(IsAccessibleGPR(reg)); 65 DCHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. 66 *gprs_[reg] = value; 69 void Arm64Context::SetFPR(uint32_t reg, uintptr_t value) { argument 70 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfDRegisters)); 71 DCHECK(IsAccessibleFPR(reg)); 72 DCHECK_NE(fprs_[reg], [all...] |
/art/runtime/arch/mips/ |
H A D | context_mips.cc | 67 void MipsContext::SetGPR(uint32_t reg, uintptr_t value) { argument 68 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); 69 DCHECK(IsAccessibleGPR(reg)); 70 CHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. 71 *gprs_[reg] = value; 74 void MipsContext::SetFPR(uint32_t reg, uintptr_t value) { argument 75 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFRegisters)); 76 DCHECK(IsAccessibleFPR(reg)); 77 CHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. 78 *fprs_[reg] [all...] |
/art/runtime/arch/mips64/ |
H A D | context_mips64.cc | 58 void Mips64Context::SetGPR(uint32_t reg, uintptr_t value) { argument 59 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters)); 60 DCHECK(IsAccessibleGPR(reg)); 61 CHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. 62 *gprs_[reg] = value; 65 void Mips64Context::SetFPR(uint32_t reg, uintptr_t value) { argument 66 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFpuRegisters)); 67 DCHECK(IsAccessibleFPR(reg)); 68 CHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. 69 *fprs_[reg] [all...] |
/art/runtime/ |
H A D | check_reference_map_visitor.h | 77 int reg = registers[i]; local 78 CHECK_LT(reg, accessor.RegistersSize()); 80 reg, number_of_dex_registers, code_info, encoding);
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H A D | common_dex_operations.h | 196 ObjPtr<mirror::Object> reg = value.GetL(); local 197 if (do_assignability_check && reg != nullptr) { 203 HandleWrapperObjPtr<mirror::Object> h_reg(hs.NewHandleWrapper(®)); 207 if (!reg->VerifierInstanceOf(field_class.Ptr())) { 212 reg->GetClass()->GetDescriptor(&temp1), 218 field->SetObj<transaction_active>(obj, reg);
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/art/compiler/optimizing/ |
H A D | locations.cc | 86 Location Location::ByteRegisterOrConstant(int reg, HInstruction* instruction) { argument 89 : Location::RegisterLocation(reg); 101 os << location.reg();
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H A D | parallel_move_test.cc | 28 static void DumpRegisterForTest(std::ostream& os, int reg) { argument 29 if (reg >= kScratchRegisterStartIndexForTest) { 30 os << "T" << reg - kScratchRegisterStartIndexForTest; 32 os << reg; local 44 DumpRegisterForTest(os, location.reg()); 82 void SpillScratch(int reg ATTRIBUTE_UNUSED) OVERRIDE {} 83 void RestoreScratch(int reg ATTRIBUTE_UNUSED) OVERRIDE {}
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/art/runtime/arch/arm/ |
H A D | context_arm.cc | 61 void ArmContext::SetGPR(uint32_t reg, uintptr_t value) { argument 62 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); 63 DCHECK(IsAccessibleGPR(reg)); 64 DCHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. 65 *gprs_[reg] = value; 68 void ArmContext::SetFPR(uint32_t reg, uintptr_t value) { argument 69 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfSRegisters)); 70 DCHECK(IsAccessibleFPR(reg)); 71 DCHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. 72 *fprs_[reg] [all...] |
/art/runtime/arch/x86/ |
H A D | context_x86.cc | 77 void X86Context::SetGPR(uint32_t reg, uintptr_t value) { argument 78 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); 79 DCHECK(IsAccessibleGPR(reg)); 80 CHECK_NE(gprs_[reg], &gZero); 81 *gprs_[reg] = value; 84 void X86Context::SetFPR(uint32_t reg, uintptr_t value) { argument 85 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFloatRegisters)); 86 DCHECK(IsAccessibleFPR(reg)); 87 CHECK_NE(fprs_[reg], reinterpret_cast<const uint32_t*>(&gZero)); 88 *fprs_[reg] [all...] |
/art/runtime/arch/x86_64/ |
H A D | context_x86_64.cc | 89 void X86_64Context::SetGPR(uint32_t reg, uintptr_t value) { argument 90 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); 91 DCHECK(IsAccessibleGPR(reg)); 92 CHECK_NE(gprs_[reg], &gZero); 93 *gprs_[reg] = value; 96 void X86_64Context::SetFPR(uint32_t reg, uintptr_t value) { argument 97 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFloatRegisters)); 98 DCHECK(IsAccessibleFPR(reg)); 99 CHECK_NE(fprs_[reg], reinterpret_cast<const uint64_t*>(&gZero)); 100 *fprs_[reg] [all...] |
/art/compiler/linker/arm64/ |
H A D | relative_patcher_arm64.h | 103 static void CheckValidReg(uint32_t reg) { argument 104 DCHECK(reg < 30u && reg != 16u && reg != 17u) << reg;
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/art/disassembler/ |
H A D | disassembler_arm64.cc | 45 const CPURegister& reg) { 47 if (reg.IsRegister() && reg.Is64Bits()) { 48 if (reg.GetCode() == TR) { 51 } else if (reg.GetCode() == LR) { 58 Disassembler::AppendRegisterNameToOutput(instr, reg); 44 AppendRegisterNameToOutput(const Instruction* instr, const CPURegister& reg) argument
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