/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | r200_fragshader.c | 48 GLuint reg0 = 0; local 76 reg0 |= (((index - GL_REG_0_ATI)*2) + 10 + useOddSrc) << (5*argPos); 79 reg0 |= (R200_TXC_ARG_A_TFACTOR_COLOR + useOddSrc) << (5*argPos); 84 reg0 |= (R200_TXC_ARG_A_TFACTOR1_COLOR + useOddSrc) << (5*argPos); 89 reg0 |= (R200_TXC_ARG_A_DIFFUSE_COLOR + useOddSrc) << (5*argPos); 92 reg0 |= (R200_TXC_ARG_A_SPECULAR_COLOR + useOddSrc) << (5*argPos); 96 reg0 |= R200_TXC_COMP_ARG_A << (4*argPos); 100 reg0 ^= R200_TXC_COMP_ARG_A << (4*argPos); 102 reg0 |= R200_TXC_BIAS_ARG_A << (4*argPos); 104 reg0 | [all...] |
/external/clang/test/OpenMP/ |
H A D | taskloop_loop_messages.cpp | 18 // register int reg0 __asm__("0"); 19 int reg0; variable 323 for (reg0 = 0; reg0 < 10; reg0 += 1) 324 c[reg0] = a[reg0];
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H A D | taskloop_simd_loop_messages.cpp | 18 // register int reg0 __asm__("0"); 19 int reg0; variable 324 for (reg0 = 0; reg0 < 10; reg0 += 1) 325 c[reg0] = a[reg0];
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H A D | for_loop_messages.cpp | 18 // register int reg0 __asm__("0"); 19 int reg0; variable 322 for (reg0 = 0; reg0 < 10; reg0 += 1) 323 c[reg0] = a[reg0];
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/external/libyuv/files/source/ |
H A D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 99 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); 110 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); 121 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); 132 res8 = (v16u8)__msa_ilvr_w((v4i32)reg4, (v4i32)reg0); 133 res9 = (v16u8)__msa_ilvl_w((v4i32)reg4, (v4i32)reg0); 166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 180 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); 191 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); 202 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg [all...] |
H A D | scale_msa.cc | 70 v8u16 reg0, reg1, reg2, reg3; local 82 reg0 = __msa_hadd_u_h(vec0, vec0); 86 reg0 += reg2; 88 reg0 = (v8u16)__msa_srari_h((v8i16)reg0, 2); 90 dst0 = (v16u8)__msa_pckev_b((v16i8)reg1, (v16i8)reg0); 133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 157 reg0 = __msa_hadd_u_h(vec0, vec0); 161 reg4 = (v8u16)__msa_pckev_d((v2i64)reg2, (v2i64)reg0); 163 reg6 = (v8u16)__msa_pckod_d((v2i64)reg2, (v2i64)reg0); 296 v4u32 reg0, reg1, reg2, reg3; local [all...] |
H A D | row_msa.cc | 481 v16u8 reg0, reg1, reg2, reg3; local 506 reg0 = (v16u8)__msa_ilvev_b((v16i8)vec1, (v16i8)vec0); 509 reg1 = (v16u8)__msa_sldi_b((v16i8)reg2, (v16i8)reg0, 11); 510 dst0 = (v16u8)__msa_vshf_b(shuffler0, (v16i8)reg3, (v16i8)reg0); 570 v8u16 reg0, reg1, reg2; local 585 reg0 = (v8u16)__msa_srai_h(vec0, 4); 591 reg0 |= reg2; 592 dst0 = (v16u8)(reg1 | reg0); 610 v8u16 reg0, reg1, reg2; local 625 reg0 774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local 826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local 1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; local 1159 v4u32 reg0, reg1, reg2, reg3; local 1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 1305 v8i16 reg0, reg1, reg2; local 1373 v4u32 reg0, reg1, reg2, reg3, rgba_scale; local 1408 v8u16 reg0; local 1433 v8u16 reg0, reg1, reg2; local 1506 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; local 1553 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local 1648 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local 1705 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local 1767 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local 1808 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local 1856 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local 1937 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local 2020 v8i16 reg0, reg1, reg2, reg3; local 2125 v8i16 reg0, reg1, reg2, reg3; local 2385 v16u8 reg0, reg1, dst0, dst1, dst2, dst3; local 2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local 2729 v4i32 reg0, reg1, reg2, reg3; local [all...] |
/external/tensorflow/tensorflow/contrib/lite/ |
H A D | model_test.cc | 164 const TfLiteRegistration& reg0 = node_and_reg0->second; local 174 ASSERT_EQ(reg0, dummy_reg);
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/external/libvpx/libvpx/vpx_dsp/mips/ |
H A D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); 58 DOTP_CONST_PAIR(reg0, reg4, cospi_16_64, cospi_16_64, reg0, reg4); 60 BUTTERFLY_4(reg4, reg0, reg2, reg6, vec1, vec3, vec2, vec0); 65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); 66 DOTP_CONST_PAIR(reg0, reg7, cospi_30_64, cospi_2_64, reg0, reg7); 71 vec0 = reg0 + reg4; 72 reg0 128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local [all...] |
H A D | idct16x16_msa.c | 15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; local 19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); 23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, 31 DOTP_CONST_PAIR(reg0, reg8, cospi_16_64, cospi_16_64, reg0, reg8); 33 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); 34 SUB4(reg2, loc1, reg14, loc0, reg6, loc3, reg10, loc2, reg0, reg12, reg4, 59 loc0 = reg0 + loc1; 60 loc1 = reg0 109 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; local [all...] |
/external/vixl/test/aarch64/ |
H A D | test-utils-aarch64.cc | 195 bool Equal64(const Register& reg0, argument 198 VIXL_ASSERT(reg0.Is64Bits() && reg1.Is64Bits()); 199 int64_t expected = core->xreg(reg0.GetCode());
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/external/swiftshader/third_party/subzero/src/ |
H A D | IceAssemblerX86BaseImpl.h | 2575 void AssemblerX86Base<TraitsType>::arith_int(Type Ty, GPRRegister reg0, 2581 emitRexRB(Ty, reg0, reg1); 2586 emitRegisterOperand(gprEncoding(reg0), gprEncoding(reg1)); 2647 void AssemblerX86Base<TraitsType>::cmp(Type Ty, GPRRegister reg0, 2649 arith_int<7>(Ty, reg0, reg1); 3748 void AssemblerX86Base<TraitsType>::xchg(Type Ty, GPRRegister reg0, argument 3754 if (reg0 == Traits::Encoded_Reg_Accumulator) { 3758 emitRexB(Ty, reg0); 3759 emitUint8(0x90 + gprEncoding(reg0)); 3761 emitRexRB(Ty, reg0, reg [all...] |
/external/v8/src/mips64/ |
H A D | macro-assembler-mips64.cc | 523 void MacroAssembler::GetNumberHash(Register reg0, Register scratch) { argument 529 xor_(reg0, reg0, scratch); 536 nor(scratch, reg0, zero_reg); 537 Lsa(reg0, scratch, reg0, 15); 540 srl(at, reg0, 12); 541 xor_(reg0, reg0, at); 544 Lsa(reg0, reg [all...] |
/external/v8/src/mips/ |
H A D | macro-assembler-mips.cc | 506 void MacroAssembler::GetNumberHash(Register reg0, Register scratch) { argument 512 xor_(reg0, reg0, scratch); 518 nor(scratch, reg0, zero_reg); 519 Lsa(reg0, scratch, reg0, 15); 522 srl(at, reg0, 12); 523 xor_(reg0, reg0, at); 526 Lsa(reg0, reg [all...] |
/external/owasp/sanitizer/tools/findbugs/lib/ |
H A D | findbugs.jar | META-INF/ META-INF/MANIFEST.MF default.xsl edu/ edu/umd/ edu/umd/cs/ edu/ ... |