| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| H A D | brw_ir_fs.h | 180 reg_offset(const fs_reg &r) function
223 !(reg_offset(r) + dr <= reg_offset(s) ||
224 reg_offset(s) + ds <= reg_offset(r));
237 reg_offset(r) >= reg_offset(s) &&
238 reg_offset(r) + dr <= reg_offset(s) + ds;
420 * fully or partially) counted from 'floor(reg_offset(ins
[all...] |
| H A D | brw_ir_vec4.h | 229 reg_offset(const backend_reg &r) function in namespace:brw
261 !(reg_offset(r) + dr <= reg_offset(s) ||
262 reg_offset(s) + ds <= reg_offset(r));
381 * fully or partially) counted from 'floor(reg_offset(inst->dst) /
389 return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE + inst->size_written,
395 * fully or partially) counted from 'floor(reg_offset(inst->src[i]) /
404 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + inst->size_read(i),
|
| H A D | brw_vec4_visitor.cpp | 1432 src_reg *reladdr, int reg_offset)
1447 * to multiply the reladdr by 2. Notice that the reg_offset part
1454 brw_imm_d(reg_offset)));
1461 brw_imm_d(reg_offset * message_header_scale)));
1465 return brw_imm_d(reg_offset * message_header_scale);
1481 int reg_offset = base_offset + orig_src.offset / REG_SIZE; local
1483 reg_offset);
1491 index = get_scratch_offset(block, inst, orig_src.reladdr, reg_offset + 1);
1510 int reg_offset = base_offset + inst->dst.offset / REG_SIZE; local
1512 reg_offset);
1431 get_scratch_offset(bblock_t *block, vec4_instruction *inst, src_reg *reladdr, int reg_offset) argument
1726 int reg_offset = base_offset + src.offset / 16; local
[all...] |
| /external/mesa3d/src/amd/common/ |
| H A D | ac_debug.c | 132 unsigned reg_offset)
134 unsigned reg = (ib[1] << 2) + reg_offset;
131 ac_parse_set_reg_packet(FILE *f, uint32_t *ib, unsigned count, unsigned reg_offset) argument
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| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_winsys.c | 665 unsigned reg_offset,
672 uint32_t reg = reg_offset + i*4;
664 radeon_read_registers(struct radeon_winsys *rws, unsigned reg_offset, unsigned num_registers, uint32_t *out) argument
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| /external/elfutils/libdw/ |
| H A D | cfi.h | 125 reg_offset, /* DW_CFA_offset_extended et al */ enumerator in enum:dwarf_frame_rule
|
| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| H A D | amdgpu_winsys.c | 460 unsigned reg_offset,
465 return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
459 amdgpu_read_registers(struct radeon_winsys *rws, unsigned reg_offset, unsigned num_registers, uint32_t *out) argument
|
| /external/mesa3d/src/amd/vulkan/ |
| H A D | radv_cmd_buffer.c | 745 unsigned reg_offset = 0, reg_count = 0; local
753 ++reg_offset;
772 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
|
| /external/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.cc | 1664 Register reg_offset = mem_op.GetRegisterOffset(); local
1669 Add(dst, base, Operand(reg_offset, extend, mem_op.GetShiftAmount()));
1672 Add(dst, base, Operand(reg_offset, shift, mem_op.GetShiftAmount()));
|
| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| H A D | sb_ir.h | 606 int reg_offset = select.sel() - array->base_gpr.sel(); local
608 reg_offset += rel->get_const_value().i;
609 return array->gpr + (reg_offset << 2);
|
| /external/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 22382 int64_t reg_offset = INT64_C(0x1087654321); local
22387 __ Mov(offset, reg_offset);
|