Searched defs:shift_type (Results 1 - 7 of 7) sorted by relevance
/external/capstone/bindings/ocaml/ |
H A D | arm.ml | 13 shift_type: int; (* TODO: covert this to pattern like arm_op_value? *) Record field in type:arm_op_shift
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H A D | arm64.ml | 8 shift_type: int; Record field in type:arm64_op_shift
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/external/v8/src/arm64/ |
H A D | disasm-arm64.cc | 1553 const char* shift_type[] = {"lsl", "lsr", "asr", "ror"}; local 1554 AppendToOutput(", %s #%" PRId32, shift_type[instr->ShiftDP()],
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/external/vixl/src/aarch64/ |
H A D | disasm-aarch64.cc | 4686 const char *shift_type[] = {"lsl", "lsr", "asr", "ror"}; local 4688 shift_type[instr->GetShiftDP()],
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H A D | simulator-aarch64.cc | 339 Shift shift_type, 353 switch (shift_type) { 1172 Shift shift_type = static_cast<Shift>(instr->GetShiftDP()); local 1176 shift_type, 337 ShiftOperand(unsigned reg_size, int64_t value, Shift shift_type, unsigned amount) const argument
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/external/v8/src/arm/ |
H A D | simulator-arm.cc | 2785 int32_t shift_type = instr->Bit(6); local 2787 if (shift_type == 0) { // LSL
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/external/valgrind/VEX/priv/ |
H A D | guest_arm_toIR.c | 9128 UInt regD = 99, regN = 99, regM = 99, imm5 = 99, shift_type = 99; local 9139 shift_type = (INSNT1(5,5) << 1) | 0; 9152 shift_type = (INSNA(6,6) << 1) | 0; 9164 dis_buf, &irt_regM_shift, NULL, irt_regM, shift_type, imm5, regM ); 9188 UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; local 9197 shift_type = (INSNT0(5,5) << 1) | 0; 9202 if (shift_type == BITS2(1,0) && imm5 == 0) 9210 shift_type = (INSNA(6,6) << 1) | 0; 9227 irt_regN, shift_type, imm5, regN ); 9246 UInt regD = 99, regN = 99, shift_type local [all...] |
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