Searched defs:src0 (Results 1 - 25 of 140) sorted by relevance

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/external/libvpx/libvpx/vp8/common/mips/msa/
H A Dcopymem_msa.c16 uint64_t src0, src1, src2, src3; local
18 LD4(src, src_stride, src0, src1, src2, src3);
19 SD4(src0, src1, src2, src3, dst, dst_stride);
24 uint64_t src0, src1, src2, src3; local
26 LD4(src, src_stride, src0, src1, src2, src3);
28 SD4(src0, src1, src2, src3, dst, dst_stride);
31 LD4(src, src_stride, src0, src1, src2, src3);
32 SD4(src0, src1, src2, src3, dst, dst_stride);
37 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
40 LD_UB8(src, src_stride, src0, src
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H A Dmfqe_msa.c21 v16i8 src0 = { 0 }; local
34 INSERT_D2_SB(src0_d, src1_d, src0);
43 UNPCK_UB_SH(src0, src_r, src_l);
72 v16i8 src0, src1, src2, src3; local
82 LD_SB4(src_ptr, src_stride, src0, src1, src2, src3);
86 UNPCK_UB_SH(src0, src_r, src_l);
/external/libvpx/libvpx/vpx_dsp/mips/
H A Dsum_squares_msa.c22 uint64_t src0, src1, src2, src3; local
26 LD4(src, src_stride, src0, src1, src2, src3);
27 INSERT_D2_SH(src0, src1, diff0);
35 v8i16 src0, src1, src2, src3, src4, src5, src6, src7; local
37 LD_SH8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7);
38 DOTP_SH2_SW(src0, src1, src0, src1, mul0, mul1);
47 v8i16 src0, src1, src2, src3, src4, src5, src6, src7; local
49 LD_SH8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7);
50 DOTP_SH2_SW(src0, src
76 v8i16 src0, src1, src2, src3, src4, src5, src6, src7; local
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H A Dsubtract_msa.c17 uint32_t src0, src1, src2, src3; local
24 LW4(src_ptr, src_stride, src0, src1, src2, src3);
26 INSERT_W4_SB(src0, src1, src2, src3, src);
37 uint64_t src0, src1, pred0, pred1; local
44 LD2(src_ptr, src_stride, src0, src1);
49 INSERT_D2_SB(src0, src1, src);
62 v16i8 src0, src1, src2, src3, src4, src5, src6, src7; local
68 LD_SB8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7);
75 ILVRL_B2_UB(src0, pred0, src_l0, src_l1);
121 v16i8 src0, src local
183 v16i8 src0, src1, src2, src3, src4, src5, src6, src7; local
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H A Dvpx_convolve_copy_msa.c19 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
23 LD_UB8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7);
26 out0 = __msa_copy_u_d((v2i64)src0, 0);
40 LD_UB4(src, src_stride, src0, src1, src2, src3);
43 out0 = __msa_copy_u_d((v2i64)src0, 0);
52 LD_UB8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7);
55 out0 = __msa_copy_u_d((v2i64)src0, 0);
71 LD_UB4(src, src_stride, src0, src1, src2, src3);
73 out0 = __msa_copy_u_d((v2i64)src0, 0);
83 LD_UB2(src, src_stride, src0, src
102 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
126 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
156 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
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H A Dvpx_convolve_avg_msa.c18 v16u8 src0, src1, src2, src3; local
23 LD_UB4(src, src_stride, src0, src1, src2, src3);
28 AVER_UB4_UB(src0, dst0, src1, dst1, src2, dst2, src3, dst3, dst0, dst1,
40 LD_UB2(src, src_stride, src0, src1);
45 AVER_UB2_UB(src0, dst0, src1, dst1, dst0, dst1);
61 v16u8 src0, src1, src2, src3; local
65 LD_UB4(src, src_stride, src0, src1, src2, src3);
69 AVER_UB4_UB(src0, dst0, src1, dst1, src2, dst2, src3, dst3, dst0, dst1,
84 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
88 LD_UB8(src, src_stride, src0, src
105 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
146 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
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/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dtest_fs_cmod_propagation.cpp105 fs_reg src0 = v->vgrf(glsl_type::float_type); local
108 bld.ADD(dest, src0, src1);
113 * 0: add(8) dest src0 src1
117 * 0: add.ge.f0(8) dest src0 src1
137 fs_reg src0 = v->vgrf(glsl_type::float_type); local
140 bld.ADD(dest, src0, src1);
145 * 0: add(8) dest src0 src1
170 fs_reg src0 = v->vgrf(glsl_type::uint_type); local
172 bld.FBL(dest, src0);
177 * 0: fbl(8) dest src0
202 fs_reg src0 = v->vgrf(glsl_type::float_type); local
241 fs_reg src0 = v->vgrf(glsl_type::float_type); local
279 fs_reg src0 = v->vgrf(glsl_type::float_type); local
283 bld.ADD(offset(dest, bld, 2), src0, src1); local
320 fs_reg src0 = v->vgrf(glsl_type::float_type); local
358 fs_reg src0 = v->vgrf(glsl_type::float_type); local
391 fs_reg src0 = v->vgrf(glsl_type::float_type); local
423 fs_reg src0 = v->vgrf(glsl_type::int_type); local
457 fs_reg src0 = v->vgrf(glsl_type::float_type); local
461 bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L); local
492 fs_reg src0 = v->vgrf(glsl_type::float_type); local
496 bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L); local
527 fs_reg src0 = v->vgrf(glsl_type::float_type); local
531 bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L); local
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H A Dtest_fs_saturate_propagation.cpp106 fs_reg src0 = v->vgrf(glsl_type::float_type); local
108 bld.ADD(dst0, src0, src1);
113 * 0: add(8) dst0 src0 src1
117 * 0: add.sat(8) dst0 src0 src1
142 fs_reg src0 = v->vgrf(glsl_type::float_type); local
144 bld.ADD(dst0, src0, src1);
146 bld.ADD(dst2, dst0, src0);
150 * 0: add(8) dst0 src0 src1
152 * 2: add(8) dst2 dst0 src0
179 fs_reg src0 local
214 fs_reg src0 = v->vgrf(glsl_type::float_type); local
248 fs_reg src0 = v->vgrf(glsl_type::float_type); local
286 fs_reg src0 = v->vgrf(glsl_type::float_type); local
325 fs_reg src0 = v->vgrf(glsl_type::float_type); local
367 fs_reg src0 = v->vgrf(glsl_type::float_type); local
409 fs_reg src0 = v->vgrf(glsl_type::float_type); local
445 fs_reg src0 = v->vgrf(glsl_type::float_type); local
484 fs_reg src0 = v->vgrf(glsl_type::float_type); local
524 fs_reg src0 = v->vgrf(glsl_type::float_type); local
527 bld.ADD(offset(dst0, bld, 2), src0, src1); local
565 fs_reg src0 = v->vgrf(glsl_type::float_type); local
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H A Dbrw_fs_builder.h281 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0) const
292 fix_math_operand(src0)));
295 return emit(instruction(opcode, dispatch_width(), dst, src0));
303 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, argument
311 fix_math_operand(src0),
315 return emit(instruction(opcode, dispatch_width(), dst, src0, src1));
324 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, argument
333 fix_3src_operand(src0),
339 src0, src1, src2));
378 * Select \p src0 i
384 emit_minmax(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod mod) const argument
507 CMP(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod condition) const argument
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H A Dbrw_vec4_builder.h246 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0) const
258 fix_math_operand(src0))));
261 return emit(instruction(opcode, dst, src0));
269 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, argument
278 fix_math_operand(src0),
282 return emit(instruction(opcode, dst, src0, src1));
290 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, argument
299 fix_3src_operand(src0),
304 return emit(instruction(opcode, dst, src0, src1, src2));
330 * Select \p src0 i
336 emit_minmax(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod mod) const argument
453 CMP(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod condition) const argument
487 IF(const src_reg &src0, const src_reg &src1, brw_conditional_mod condition) const argument
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/external/swiftshader/src/Shader/
H A DPixelPipeline.cpp87 const Src &src0 = instruction->src[0]; local
100 if(src0.type != Shader::PARAMETER_VOID) s0 = fetchRegister(src0);
104 Float4 x = shaderModel < 0x0104 ? v[2 + dst.index].x : v[2 + src0.index].x;
105 Float4 y = shaderModel < 0x0104 ? v[2 + dst.index].y : v[2 + src0.index].y;
106 Float4 z = shaderModel < 0x0104 ? v[2 + dst.index].z : v[2 + src0.index].z;
107 Float4 w = shaderModel < 0x0104 ? v[2 + dst.index].w : v[2 + src0.index].w;
135 if((src0.swizzle & 0x30) == 0x20) // .xyz
137 TEXCRD(d, x, y, z, src0.index, src0
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/external/webp/src/dsp/
H A Dlossless_enc_msa.c21 #define TRANSFORM_COLOR_8(src0, src1, dst0, dst1, c0, c1, mask0, mask1) do { \
24 VSHF_B2_SH(src0, src0, src1, src1, mask0, mask0, g0, g1); \
27 t0 = __msa_subv_h((v8i16)src0, t0); \
29 t4 = __msa_srli_w((v4i32)src0, 16); \
34 VSHF_B2_UB(src0, t0, src1, t1, mask1, mask1, dst0, dst1); \
53 v16u8 src0, dst0; local
64 LD_UB2(data, 4, src0, src1);
65 TRANSFORM_COLOR_8(src0, src1, dst0, dst1, g2br, r2b, mask0, mask1);
72 src0
101 v16u8 src0, dst0, tmp0; local
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/external/libvpx/libvpx/vp9/common/mips/msa/
H A Dvp9_mfqe_msa.c21 v16i8 src0 = { 0 }; local
34 INSERT_D2_SB(src0_d, src1_d, src0);
43 UNPCK_UB_SH(src0, src_r, src_l);
72 v16i8 src0, src1, src2, src3, dst0, dst1, dst2, dst3; local
79 LD_SB4(src_ptr, src_stride, src0, src1, src2, src3);
83 UNPCK_UB_SH(src0, src_r, src_l);
/external/mesa3d/src/compiler/nir/
H A Dnir_lower_indirect_derefs.c80 nir_phi_src *src0 = ralloc(phi, nir_phi_src); local
81 src0->pred = nir_if_last_then_block(if_stmt);
82 src0->src = nir_src_for_ssa(then_dest);
83 exec_list_push_tail(&phi->srcs, &src0->node);
H A Dnir_lower_double_ops.c442 lower_mod(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1) argument
450 nir_ssa_def *floor = nir_ffloor(b, nir_fdiv(b, src0, src1));
451 nir_ssa_def *mod = nir_fsub(b, src0, nir_fmul(b, src1, floor));
H A Dnir_lower_wpos_ytransform.c72 nir_cmp(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) argument
74 return nir_bcsel(b, nir_flt(b, src0, nir_imm_float(b, 0.0)), src1, src2);
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_quad.c162 * src0 src1
164 * # 0 | 1 # # 4 | 5 # # 0 | 1 | 4 | 5 # src0
195 LLVMValueRef src0, src1; local
197 src0 = LLVMBuildBitCast(builder, src[i + 0], type2_ref, "");
200 dst[i + 0] = lp_build_interleave2(gallivm, type2, src0, src1, 0);
201 dst[i + 1] = lp_build_interleave2(gallivm, type2, src0, src1, 1);
H A Dlp_bld_tgsi_info.c404 struct lp_tgsi_channel_info src0; local
407 analyse_src(ctx, &src0, &inst->Src[0].Register, chan);
410 if (is_immediate(&src0, 0.0f)) {
411 res[chan] = src0;
414 } else if (is_immediate(&src0, 1.0f)) {
417 res[chan] = src0;
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_lowering_gm107.cpp47 Value *src0; local
53 src0 = bld.getSSA();
56 bld.mkOp2(OP_ADD , TYPE_U32, src0, i->getSrc(0), i->getSrc(1));
58 bld.mkOp1(OP_MOV , TYPE_U32, src0, i->getSrc(0));
60 i->setSrc(0, src0);
/external/libvpx/libvpx/vpx_dsp/x86/
H A Dvariance_sse2.c46 const __m128i src0 = _mm_unpacklo_epi8(READ64(src, src_stride, 0), zero); local
50 const __m128i diff0 = _mm_sub_epi16(src0, ref0);
76 const __m128i src0 = _mm_unpacklo_epi8( local
80 const __m128i diff0 = _mm_sub_epi16(src0, ref0);
118 const __m128i src0 = _mm_unpacklo_epi8(s, zero); local
120 const __m128i diff0 = _mm_sub_epi16(src0, ref0);
/external/libyuv/files/source/
H A Drotate_msa.cc84 v16u8 src0, src1, src2, src3, dst0, dst1, dst2, dst3, vec0, vec1, vec2, vec3; local
90 src0 = (v16u8)__msa_ld_b((v16i8*)s, 0);
98 ILVRL_B(src0, src1, src2, src3, vec0, vec1, vec2, vec3);
100 src0 = (v16u8)__msa_ld_b((v16i8*)s, 0);
108 ILVRL_B(src0, src1, src2, src3, vec0, vec1, vec2, vec3);
112 src0 = (v16u8)__msa_ld_b((v16i8*)s, 0);
120 ILVRL_B(src0, src1, src2, src3, vec0, vec1, vec2, vec3);
122 src0 = (v16u8)__msa_ld_b((v16i8*)s, 0);
130 ILVRL_B(src0, src1, src2, src3, vec0, vec1, vec2, vec3);
165 v16u8 src0, src local
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/external/mesa3d/src/compiler/spirv/
H A Dvtn_alu.c65 struct vtn_ssa_value *src0 = wrap_matrix(b, _src0); local
70 unsigned src0_rows = glsl_get_vector_elements(src0->type);
71 unsigned src0_columns = glsl_get_matrix_columns(src0->type);
76 dest_type = glsl_matrix_type(glsl_get_base_type(src0->type),
79 dest_type = glsl_vector_type(glsl_get_base_type(src0->type), src0_rows);
89 src0 = src1_transpose;
96 glsl_get_base_type(src0->type) == GLSL_TYPE_FLOAT) {
97 /* We already have the rows of src0 and the columns of src1 available,
111 /* We don't handle the case where src1 is transposed but not src0, since
117 /* dest[i] = sum(src0[
155 vtn_handle_matrix_alu(struct vtn_builder *b, SpvOp opcode, struct vtn_value *dest, struct vtn_ssa_value *src0, struct vtn_ssa_value *src1) argument
[all...]
/external/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_scan.c315 const struct tgsi_full_src_register *src0 = &fullinst->Src[0]; local
320 if (src0->Register.Indirect && src0->Indirect.ArrayID)
321 input = info->input_array_first[src0->Indirect.ArrayID];
323 input = src0->Register.Index;
/external/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_emit.c116 uint saturate, uint src0, uint src1, uint src2)
125 if (GET_UREG_TYPE(src0) == REG_TYPE_CONST)
140 s[0] = src0;
156 src0 = s[0];
163 *(p->csr++) = (op | A0_DEST(dest) | mask | saturate | A0_SRC0(src0));
164 *(p->csr++) = (A1_SRC0(src0) | A1_SRC1(src1));
227 coord, 0, 0 ); /* src0, src1, src2 */
112 i915_emit_arith(struct i915_fp_compile * p, uint op, uint dest, uint mask, uint saturate, uint src0, uint src1, uint src2) argument
/external/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_qpu_emit.c165 struct qpu_reg *src0, struct qpu_reg *src1,
168 uint32_t mux0 = src0->mux == QPU_MUX_SMALL_IMM ? QPU_MUX_B : src0->mux;
173 (src0->addr == src1->addr &&
174 src0->mux == src1->mux)) {
178 if (swap_file(src0) || swap_file(src1))
186 queue(block, qpu_a_FMAX(qpu_rb(14), *src0, *src0));
188 queue(block, qpu_a_MOV(qpu_rb(14), *src0));
197 *src0
163 fixup_raddr_conflict(struct qblock *block, struct qpu_reg dst, struct qpu_reg *src0, struct qpu_reg *src1, struct qinst *inst, uint64_t *unpack) argument
[all...]

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