| /art/compiler/utils/x86/ |
| H A D | jni_macro_assembler_x86.cc | 364 ManagedRegister /*src_base*/,
383 FrameOffset src_base,
389 __ movl(scratch, Address(ESP, src_base));
382 Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister mscratch, size_t size) argument
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| /art/compiler/utils/x86_64/ |
| H A D | jni_macro_assembler_x86_64.cc | 415 ManagedRegister /*src_base*/,
434 FrameOffset src_base,
440 __ movq(scratch, Address(CpuRegister(RSP), src_base));
433 Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister mscratch, size_t size) argument
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| /art/compiler/utils/arm64/ |
| H A D | jni_macro_assembler_arm64.cc | 406 ManagedRegister src_base,
411 Arm64ManagedRegister base = src_base.AsArm64();
450 FrameOffset /*src_base*/,
405 Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister m_scratch, size_t size) argument
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| /art/compiler/optimizing/ |
| H A D | intrinsics_mips64.cc | 2168 GpuRegister src_base = locations->GetTemp(1).AsRegister<GpuRegister>(); local
2217 __ Daddiu64(src_base, src, data_offset + char_size * src_pos_const, TMP);
2219 __ Daddiu64(src_base, src, data_offset, TMP);
2220 __ Dlsa(src_base, src_pos.AsRegister<GpuRegister>(), src_base, char_shift);
2232 __ Lh(TMP, src_base, 0);
2233 __ Daddiu(src_base, src_base, char_size);
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| H A D | intrinsics_arm64.cc | 2250 // source address for System.arraycopy* intrinsics in `src_base`,
2259 const Register& src_base,
2271 __ Add(src_base, src, element_size * constant + data_offset);
2273 __ Add(src_base, src, data_offset);
2274 __ Add(src_base, src_base, Operand(XRegisterFrom(src_pos), LSL, element_size_shift));
2287 __ Add(src_end, src_base, element_size * constant);
2289 __ Add(src_end, src_base, Operand(XRegisterFrom(copy_length), LSL, element_size_shift));
2840 // source address for System.arraycopy* intrinsics in `src_base`,
2881 // source address for System.arraycopy* intrinsics in `src_base`,
2252 GenSystemArrayCopyAddresses(MacroAssembler* masm, DataType::Type type, const Register& src, const Location& src_pos, const Register& dst, const Location& dst_pos, const Location& copy_length, const Register& src_base, const Register& dst_base, const Register& src_end) argument
[all...] |
| H A D | intrinsics_mips.cc | 3066 Register src_base = locations->GetTemp(1).AsRegister<Register>(); local
3114 __ Addiu32(src_base, src, data_offset + char_size * src_pos_const, TMP);
3116 __ Addiu32(src_base, src, data_offset, TMP);
3117 __ ShiftAndAdd(src_base, src_pos.AsRegister<Register>(), src_base, char_shift);
3129 __ Lh(TMP, src_base, 0);
3130 __ Addiu(src_base, src_base, char_size);
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| H A D | intrinsics_x86.cc | 1257 Register src_base = locations->GetTemp(0).AsRegister<Register>(); local
1258 DCHECK_EQ(src_base, ESI);
1293 // Validity checks: source. Use src_base as a temporary register.
1294 CheckPosition(assembler, srcPos, src, Location::RegisterLocation(count), slow_path, src_base);
1296 // Validity checks: dest. Use src_base as a temporary register.
1297 CheckPosition(assembler, destPos, dest, Location::RegisterLocation(count), slow_path, src_base);
1308 __ leal(src_base, Address(src, char_size * srcPos_const + data_offset));
1310 __ leal(src_base, Address(src, srcPos.AsRegister<Register>(),
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| H A D | intrinsics_x86_64.cc | 1037 CpuRegister src_base = locations->GetTemp(0).AsRegister<CpuRegister>(); local
1038 DCHECK_EQ(src_base.AsRegister(), RSI);
1066 // Validity checks: source. Use src_base as a temporary register.
1067 CheckPosition(assembler, src_pos, src, length, slow_path, src_base);
1069 // Validity checks: dest. Use src_base as a temporary register.
1070 CheckPosition(assembler, dest_pos, dest, length, slow_path, src_base);
1088 __ leal(src_base, Address(src, char_size * src_pos_const + data_offset));
1090 __ leal(src_base, Address(src, src_pos.AsRegister<CpuRegister>(),
1119 // source address for the System.arraycopy intrinsic in `src_base`,
1128 const CpuRegister& src_base,
1121 GenSystemArrayCopyAddresses(X86_64Assembler* assembler, DataType::Type type, const CpuRegister& src, const Location& src_pos, const CpuRegister& dst, const Location& dst_pos, const Location& copy_length, const CpuRegister& src_base, const CpuRegister& dst_base, const CpuRegister& src_end) argument
[all...] |
| /art/compiler/utils/mips/ |
| H A D | assembler_mips.cc | 703 Register src_base,
707 CHECK_NE(src_base, tmp);
710 Addu(dst, src_base, src_idx);
712 Lsa(dst, src_idx, src_base, shamt);
715 Addu(dst, src_base, tmp);
5051 void MipsAssembler::Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, argument
5055 LoadFromOffset(kLoadWord, scratch, src_base.AsMips().AsCoreRegister(), src_offset.Int32Value());
5068 FrameOffset src_base ATTRIBUTE_UNUSED,
701 ShiftAndAdd(Register dst, Register src_idx, Register src_base, int shamt, Register tmp) argument
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.cc | 3859 void Mips64Assembler::Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, argument
3864 LoadFromOffset(kLoadWord, scratch, src_base.AsMips64().AsGpuRegister(),
3868 LoadFromOffset(kLoadDoubleword, scratch, src_base.AsMips64().AsGpuRegister(),
3894 FrameOffset src_base ATTRIBUTE_UNUSED,
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