| /art/runtime/ |
| H A D | common_dex_operations.h | 209 std::string temp1, temp2, temp3; local
212 reg->GetClass()->GetDescriptor(&temp1),
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| /art/runtime/interpreter/ |
| H A D | interpreter_switch_impl.cc | 416 std::string temp1, temp2; local
419 obj_result->GetClass()->GetDescriptor(&temp1),
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| H A D | interpreter_common.cc | 1344 std::string temp1, temp2; local
1348 o->GetClass()->GetDescriptor(&temp1),
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| /art/compiler/optimizing/ |
| H A D | code_generator_mips64.cc | 568 GpuRegister temp1)
573 temp1_(temp1) {
2570 GpuRegister temp1 = locations->GetTemp(0).AsRegister<GpuRegister>();
2603 // /* HeapReference<Class> */ temp1 = obj->klass_
2604 __ LoadFromOffset(kLoadUnsignedWord, temp1, obj, class_offset, null_checker);
2605 __ MaybeUnpoisonHeapReference(temp1);
2607 // /* HeapReference<Class> */ temp1 = temp1->component_type_
2608 __ LoadFromOffset(kLoadUnsignedWord, temp1, temp1, component_offse
564 ReadBarrierMarkAndUpdateFieldSlowPathMIPS64(HInstruction* instruction, Location ref, GpuRegister obj, Location field_offset, GpuRegister temp1) argument
[all...] |
| H A D | intrinsics_mips64.cc | 1667 GpuRegister temp1 = locations->GetTemp(0).AsRegister<GpuRegister>(); local
1707 __ Lw(temp1, str, class_offset);
1709 __ Bnec(temp1, temp2, &return_false);
1713 __ Lw(temp1, str, count_offset);
1717 __ Bnec(temp1, temp2, &return_false);
1721 __ Beqzc(temp1, &return_true);
1733 __ Dext(temp2, temp1, 0, 1); // Extract compression flag.
1734 __ Srl(temp1, temp1, 1); // Extract length.
1735 __ Sllv(temp1, temp
[all...] |
| H A D | intrinsics_arm64.cc | 1319 Register temp1 = WRegisterFrom(locations->GetTemp(1)); local
1357 __ Lsr(temp1, temp2, 1u);
1361 __ Ldr(temp1, HeapOperand(arg, count_offset));
1364 __ Subs(out, temp0, temp1);
1366 __ Csel(temp0, temp1, temp0, ge);
1379 __ Mov(temp1, value_offset);
1401 __ Ldr(temp4, MemOperand(str.X(), temp1.X()));
1402 __ Ldr(temp2, MemOperand(arg.X(), temp1.X()));
1405 __ Add(temp1, temp1, char_siz
1565 Register temp1 = scratch_scope.AcquireW(); local
2475 Register temp1 = WRegisterFrom(locations->GetTemp(0)); local
[all...] |
| H A D | intrinsics_arm_vixl.cc | 528 const vixl32::Register temp1 = temps.Acquire(); local
552 __ Vmov(temp1, op1);
555 __ Orr(temp1, temp1, temp2);
557 __ And(temp1, temp1, temp2);
559 __ Vmov(out, temp1);
564 __ Movt(temp1, High16Bits(kNanFloat)); // 0x7FC0xxxx is a NaN.
565 __ Vmov(out, temp1);
807 vixl32::SRegister temp1 local
1481 const vixl32::Register temp1 = RegisterFrom(locations->GetTemp(1)); local
1578 const vixl32::Register temp1 = RegisterFrom(locations->GetTemp(1)); local
1888 vixl32::Register temp1 = RegisterFrom(locations->GetTemp(1)); local
1923 vixl32::Register temp1 = RegisterFrom(locations->GetTemp(1)); local
2227 vixl32::Register temp1 = RegisterFrom(temp1_loc); local
2530 GenSystemArrayCopyBaseAddress(GetAssembler(), type, src, src_pos, temp1); local
2532 GenSystemArrayCopyEndAddress(GetAssembler(), type, length, temp1, temp3); local
2572 GenSystemArrayCopyBaseAddress(GetAssembler(), type, src, src_pos, temp1); local
2576 GenSystemArrayCopyEndAddress(GetAssembler(), type, length, temp1, temp3); local
[all...] |
| H A D | intrinsics_mips.cc | 2092 Register temp1 = locations->GetTemp(0).AsRegister<Register>(); local
2131 __ Lw(temp1, str, class_offset);
2133 __ Bne(temp1, temp2, &return_false);
2137 __ Lw(temp1, str, count_offset);
2141 __ Bne(temp1, temp2, &return_false);
2145 __ Beqz(temp1, &return_true);
2159 __ Ext(temp2, temp1, 0, 1);
2161 __ Sll(temp2, temp1, 31);
2164 __ Srl(temp1, temp1,
[all...] |
| H A D | intrinsics_x86.cc | 109 Register temp1 = temp1_loc.AsRegister<Register>(); variable
114 // In this code path, registers `temp1`, `temp2`, and `temp3`
125 __ xorl(temp1, temp1);
132 __ movl(temp2, Address(src, temp1, ScaleFactor::TIMES_4, adjusted_offset));
134 __ leal(temp2, Address(src_pos.AsRegister<Register>(), temp1, ScaleFactor::TIMES_1, 0));
155 __ movl(Address(dest, temp1, ScaleFactor::TIMES_4, adjusted_offset), temp2);
157 __ leal(temp3, Address(dest_pos.AsRegister<Register>(), temp1, ScaleFactor::TIMES_1, 0));
161 __ addl(temp1, Immediate(1));
219 XmmRegister temp1 local
2213 XmmRegister temp1 = locations->GetTemp(0).AsFpuRegister<XmmRegister>(); local
2218 __ movsd(Address(base, offset, ScaleFactor::TIMES_1, 0), temp1); local
2351 Register temp1 = temp1_loc.AsRegister<Register>(); local
2913 Register temp1 = temp1_loc.AsRegister<Register>(); local
3169 GenSystemArrayCopyBaseAddress(GetAssembler(), type, src, src_pos, temp1); local
3185 GenSystemArrayCopyEndAddress(GetAssembler(), type, length, temp1, temp3); local
3260 GenSystemArrayCopyEndAddress(GetAssembler(), type, length, temp1, temp3); local
[all...] |
| H A D | intrinsics_x86_64.cc | 1179 CpuRegister temp1 = temp1_loc.AsRegister<CpuRegister>(); local
1258 temp1,
1267 temp1,
1278 // /* HeapReference<Class> */ temp1 = dest->klass_
1281 // Register `temp1` is not trashed by the read barrier emitted
1285 // temporaries such a `temp1`.
1289 // If heap poisoning is enabled, `temp1` and `temp2` have been
1293 // /* HeapReference<Class> */ temp1 = dest->klass_
1294 __ movl(temp1, Address(dest, class_offset));
1301 __ MaybeUnpoisonHeapReference(temp1);
1414 GetAssembler(), type, src, src_pos, dest, dest_pos, length, temp1, temp2, temp3); local
2422 CpuRegister temp1 = locations->GetTemp(0).AsRegister<CpuRegister>(); local
2600 CpuRegister temp1 = locations->GetTemp(0).AsRegister<CpuRegister>(); local
[all...] |
| H A D | code_generator_arm64.cc | 3522 Register temp1 = temps.AcquireX(); local
3524 __ Ldr(temp1, MemOperand(sp, 0));
3525 __ Ldrh(temp2, MemOperand(temp1, ArtMethod::HotnessCountOffset().Int32Value()));
3527 __ Strh(temp2, MemOperand(temp1, ArtMethod::HotnessCountOffset().Int32Value()));
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| H A D | code_generator_arm_vixl.cc | 1023 vixl32::Register temp1,
1032 temp1_(temp1),
4395 vixl32::Register temp1 = RegisterFrom(locations->GetTemp(0)); local
4404 __ Mov(temp1, static_cast<int32_t>(magic));
4405 __ Smull(temp2, temp1, dividend, temp1);
4408 __ Add(temp1, temp1, dividend);
4410 __ Sub(temp1, temp1, dividen
1015 LoadReferenceWithBakerReadBarrierAndUpdateFieldSlowPathARMVIXL( HInstruction* instruction, Location ref, vixl32::Register obj, uint32_t offset, Location index, ScaleFactor scale_factor, bool needs_null_check, vixl32::Register temp1, vixl32::Register temp2, Location entrypoint = Location::NoLocation()) argument
5370 GenerateWideAtomicStore(vixl32::Register addr, uint32_t offset, vixl32::Register value_lo, vixl32::Register value_hi, vixl32::Register temp1, vixl32::Register temp2, HInstruction* instruction) argument
6395 vixl32::Register temp1 = RegisterFrom(temp1_loc); local
6928 vixl32::Register temp1 = temps.Acquire(); local
7008 vixl32::DRegister temp1 = temps.AcquireD(); local
[all...] |
| H A D | code_generator_mips.cc | 612 Register temp1)
617 temp1_(temp1) {
2989 Register temp1 = locations->GetTemp(0).AsRegister<Register>(); local
3024 // /* HeapReference<Class> */ temp1 = obj->klass_
3025 __ LoadFromOffset(kLoadWord, temp1, obj, class_offset, null_checker);
3026 __ MaybeUnpoisonHeapReference(temp1);
3028 // /* HeapReference<Class> */ temp1 = temp1->component_type_
3029 __ LoadFromOffset(kLoadWord, temp1, temp1, component_offse
608 ReadBarrierMarkAndUpdateFieldSlowPathMIPS(HInstruction* instruction, Location ref, Register obj, Location field_offset, Register temp1) argument
[all...] |
| H A D | code_generator_x86.cc | 4980 XmmRegister temp1 = locations->GetTemp(0).AsFpuRegister<XmmRegister>(); local
4982 __ movd(temp1, value.AsRegisterPairLow<Register>());
4984 __ punpckldq(temp1, temp2);
4985 __ movsd(Address(base, offset), temp1); local
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| H A D | code_generator_x86_64.cc | 555 CpuRegister temp1,
562 temp1_(temp1),
6630 CpuRegister* temp1,
6689 DCHECK(temp1 != nullptr);
6692 instruction, ref, obj, src, /* unpoison_ref_before_marking */ true, *temp1, *temp2);
550 ReadBarrierMarkAndUpdateFieldSlowPathX86_64(HInstruction* instruction, Location ref, CpuRegister obj, const Address& field_addr, bool unpoison_ref_before_marking, CpuRegister temp1, CpuRegister temp2) argument
6624 GenerateReferenceLoadWithBakerReadBarrier(HInstruction* instruction, Location ref, CpuRegister obj, const Address& src, bool needs_null_check, bool always_update_field, CpuRegister* temp1, CpuRegister* temp2) argument
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| /art/runtime/mirror/ |
| H A D | class.cc | 435 std::string temp1, temp2; local
436 return IsInSamePackage(klass1->GetDescriptor(&temp1), klass2->GetDescriptor(&temp2));
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