Searched defs:tmp_reg (Results 1 - 5 of 5) sorted by relevance

/art/compiler/utils/arm/
H A Dassembler_arm_vixl.cc251 vixl32::Register tmp_reg; local
259 tmp_reg = temps.Acquire();
267 tmp_reg = (base.GetCode() != 5) ? r5 : r6;
268 ___ Push(tmp_reg);
275 offset = AdjustLoadStoreOffset(GetAllowedStoreOffsetBits(type), tmp_reg, base, offset);
276 base = tmp_reg;
296 if ((tmp_reg.IsValid()) && (tmp_reg.GetCode() != kIpCode)) {
297 CHECK(tmp_reg.Is(r5) || tmp_reg
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/art/compiler/optimizing/
H A Dintrinsics_mips64.cc1767 GpuRegister tmp_reg = start_at_zero ? locations->GetTemp(0).AsRegister<GpuRegister>() : TMP; local
1789 __ LoadConst32(tmp_reg, std::numeric_limits<uint16_t>::max());
1792 __ Bltuc(tmp_reg, char_reg, slow_path->GetEntryLabel()); // UTF-16 required
1796 DCHECK_EQ(tmp_reg, A2);
1798 __ Clear(tmp_reg);
H A Dintrinsics_arm64.cc181 Register tmp_reg = WRegisterFrom(tmp_); variable
186 __ Ldr(tmp_reg, MemOperand(src_curr_addr, element_size, PostIndex));
187 codegen->GetAssembler()->MaybeUnpoisonHeapReference(tmp_reg); variable
189 // tmp_reg = ReadBarrier::Mark(tmp_reg);
212 codegen->GetAssembler()->MaybePoisonHeapReference(tmp_reg); variable
213 __ Str(tmp_reg, MemOperand(dst_curr_addr, element_size, PostIndex));
1742 Register tmp_reg = WRegisterFrom(locations->GetTemp(0)); local
1743 __ Mov(tmp_reg, 0);
H A Dintrinsics_arm_vixl.cc1991 vixl32::Register tmp_reg = RegisterFrom(locations->GetTemp(0)); local
1992 DCHECK(tmp_reg.Is(r2));
1994 __ Mov(tmp_reg, 0);
H A Dintrinsics_mips.cc2197 Register tmp_reg = start_at_zero ? locations->GetTemp(0).AsRegister<Register>() : TMP; local
2227 __ LoadConst32(tmp_reg, std::numeric_limits<uint16_t>::max());
2230 __ Bltu(tmp_reg, char_reg, slow_path->GetEntryLabel());
2234 DCHECK_EQ(tmp_reg, A2);
2236 __ Clear(tmp_reg);

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