Searched defs:writemask (Results 1 - 25 of 46) sorted by relevance

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/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_opcodes.c530 unsigned int writemask,
543 if (!writemask)
548 srcmasks[src] |= writemask;
551 srcmasks[src] |= writemask;
528 rc_compute_sources_for_writemask( const struct rc_instruction *inst, unsigned int writemask, unsigned int *srcmasks) argument
H A Dradeon_rename_regs.c72 unsigned writemask; local
86 writemask = rc_variable_writemask_sum(var);
87 rc_variable_change_dst(var, new_index, writemask);
H A Dradeon_compiler.c170 * writemask is honoured.
172 void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask) argument
184 inst->U.I.DstReg.WriteMask &= writemask;
H A Dradeon_variable.c39 * Rewrite the index and writemask for the destination register of var
321 unsigned int writemask; local
335 writemask = sub_inst->WriteMask;
338 writemask = sub_inst->OutputWriteMask;
340 writemask = 0;
343 new_var = rc_variable(c, file, sub_inst->DestIndex, writemask,
393 unsigned int writemask = 0; local
395 writemask |= var->Dst.WriteMask;
398 return writemask;
H A Dradeon_pair_regalloc.c289 unsigned int writemask,
299 if (classes[i].Writemasks[j] == writemask) {
332 unsigned int writemask = rc_variable_writemask_sum(variable); local
344 writemask = RC_MASK_XYZW;
350 class_index = find_class(classes, writemask, 3);
365 writemask, c.Writemasks[i]);
372 * then the writemask will be set to RC_MASK_XYZW
435 class_index = find_class(classes, writemask,
444 variable->Dst.Index, writemask);
474 static int get_reg_id(unsigned int index, unsigned int writemask) argument
287 find_class( const struct rc_class * classes, unsigned int writemask, unsigned int max_writemask_count) argument
560 unsigned int chan, writemask = 0; local
628 unsigned int writemask = reg_get_writemask(reg); local
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/external/mesa3d/src/compiler/glsl/
H A Dir_builder.h29 enum writemask { enum in namespace:ir_builder
124 ir_assignment *assign(deref lhs, operand rhs, int writemask);
126 ir_assignment *assign(deref lhs, operand rhs, operand condition, int writemask);
H A Dir_builder.cpp49 assign(deref lhs, operand rhs, operand condition, int writemask) argument
56 writemask);
68 assign(deref lhs, operand rhs, int writemask) argument
70 return assign(lhs, rhs, (ir_rvalue *) NULL, writemask);
/external/mesa3d/src/gallium/drivers/softpipe/
H A Dsp_buffer.c144 if (params->writemask & (1 << c)) {
163 unsigned writemask,
269 if (writemask & (1 << c)) {
328 opcode, params->writemask, rgba, rgba2);
158 handle_op_uint(const struct pipe_shader_buffer *bview, bool just_read, unsigned char *data_ptr, uint qi, unsigned opcode, unsigned writemask, float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE], float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE]) argument
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_fs_vector_splitting.cpp262 unsigned int writemask; local
269 writemask = 1;
272 writemask = 1 << i;
285 NULL, writemask));
H A Dbrw_ir_vec4.h160 unsigned writemask);
162 unsigned writemask);
202 writemask(dst_reg reg, unsigned mask) function in namespace:brw
205 assert((reg.writemask & mask) != 0);
206 reg.writemask &= mask;
H A Dbrw_vec4_tcs.cpp213 brw_imm_ud(dst.writemask << first_component), indirect_offset);
222 /* Read into a temporary and copy with a swizzle and writemask. */
231 unsigned writemask,
235 if (writemask == 0)
242 brw_imm_ud(writemask), indirect_offset);
283 * honoring the writemask
302 dst.writemask = brw_writemask_for_size(instr->num_components);
306 dst.writemask = brw_writemask_for_size(instr->num_components);
321 dst.writemask = brw_writemask_for_size(instr->num_components);
348 * need to fix the writemask i
230 emit_urb_write(const src_reg &value, unsigned writemask, unsigned base_offset, const src_reg &indirect_offset) argument
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H A Dbrw_reg.h143 * read from a swizzled source given the instruction writemask.
262 unsigned writemask:4; /* dest only, align16 only */ member in struct:brw_reg::__anon17115::__anon17116
351 * \param writemask WRITEMASK_X/Y/Z/W bitfield
364 unsigned writemask)
386 * set swizzle and writemask to W, as the lower bits of subnr will
392 reg.writemask = writemask;
769 /* If/else instructions break in align16 mode if writemask & swizzle
973 reg.writemask &= mask;
981 reg.writemask
354 brw_reg(enum brw_reg_file file, unsigned nr, unsigned subnr, unsigned negate, unsigned abs, enum brw_reg_type type, unsigned vstride, unsigned width, unsigned hstride, unsigned swizzle, unsigned writemask) argument
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/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_aos.c313 LLVMValueRef writemask; local
315 writemask = lp_build_const_mask_aos_swizzled(bld->bld_base.base.gallivm,
322 mask = LLVMBuildAnd(builder, mask, writemask, "");
324 mask = writemask;
491 * assume a full writemask and then let LLVM optimization passes eliminate
/external/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_transform.h226 unsigned file, unsigned index, unsigned writemask)
230 reg->Register.WriteMask = writemask;
225 tgsi_transform_dst_reg(struct tgsi_full_dst_register *reg, unsigned file, unsigned index, unsigned writemask) argument
H A Dtgsi_scan.h173 ubyte writemask; member in struct:tgsi_array_info
H A Dtgsi_exec.h144 unsigned writemask; member in struct:tgsi_buffer_params
H A Dtgsi_text.c443 uint *writemask )
451 *writemask = TGSI_WRITEMASK_NONE;
455 *writemask |= TGSI_WRITEMASK_X;
459 *writemask |= TGSI_WRITEMASK_Y;
463 *writemask |= TGSI_WRITEMASK_Z;
467 *writemask |= TGSI_WRITEMASK_W;
470 if (*writemask == TGSI_WRITEMASK_NONE) {
478 *writemask = TGSI_WRITEMASK_XYZW;
812 uint writemask; local
825 if (!parse_opt_writemask( ctx, &writemask ))
1314 uint writemask; local
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/external/mesa3d/src/gallium/auxiliary/util/
H A Du_simple_shaders.c210 * IMM {0,0,0,1} // (if writemask != 0xf)
211 * MOV TEMP[0], IMM[0] // (if writemask != 0xf)
212 * TEX TEMP[0].writemask, IN[0], SAMP[0], 2D;
219 * \param writemask mask of TGSI_WRITEMASK_x
225 unsigned writemask,
257 if (writemask != TGSI_WRITEMASK_XYZW) {
265 ureg_writemask(temp, writemask),
269 ureg_writemask(temp, writemask),
222 util_make_fragment_tex_shader_writemask(struct pipe_context *pipe, unsigned tex_target, unsigned interp_mode, unsigned writemask, enum tgsi_return_type stype, enum tgsi_return_type dtype) argument
H A Du_blit.c162 set_fragment_shader(struct blit_state *ctx, uint writemask, argument
180 if (!ctx->fs[pipe_tex][writemask][idx]) {
185 ctx->fs[pipe_tex][writemask][idx] =
188 writemask,
192 cso_set_fragment_shader_handle(ctx->cso, ctx->fs[pipe_tex][writemask][idx]);
360 * \param writemask bitmask of PIPE_MASK_[RGBAZS]. Controls which channels
375 uint writemask)
406 blit_depth = is_depth && (writemask & PIPE_MASK_Z);
407 blit_stencil = is_stencil && (writemask & PIPE_MASK_S);
410 assert((writemask
365 util_blit_pixels(struct blit_state *ctx, struct pipe_resource *src_tex, unsigned src_level, int srcX0, int srcY0, int srcX1, int srcY1, int srcZ0, struct pipe_surface *dst, int dstX0, int dstY0, int dstX1, int dstY1, float z, uint filter, uint writemask) argument
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/external/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_translate.c323 * Compute flags for saturation and writemask.
498 uint writemask; local
664 A0_DEST_CHANNEL_ALL, /* dest writemask */
677 A0_DEST_CHANNEL_ALL, /* dest writemask */
841 writemask = inst->Dst[0].Register.WriteMask;
843 if (writemask & TGSI_WRITEMASK_Y) {
846 if (writemask & TGSI_WRITEMASK_X)
865 if (writemask & TGSI_WRITEMASK_X) {
H A Di915_state.c469 int writemask = depth_stencil->stencil[0].writemask & 0xff; local
475 STENCIL_WRITE_MASK(writemask));
498 int wmask = depth_stencil->stencil[1].writemask & 0xff;
534 if (depth_stencil->depth.writemask)
/external/mesa3d/src/gallium/drivers/ilo/shader/
H A Dtoy_compiler_asm.c50 unsigned writemask; member in struct:codegen::codegen_dst
637 /* the lower 4 bits are reserved for the writemask */
642 dst->writemask;
652 assert(dst->writemask == TOY_WRITEMASK_XYZW);
680 dst->writemask;
683 assert(dst->writemask == TOY_WRITEMASK_XYZW);
842 dst->writemask << 17 |
855 dst->writemask << 17 |
1012 translate_writemask(enum toy_writemask writemask) argument
1015 assert(writemask <
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/external/mesa3d/src/compiler/nir/
H A Dnir_builder.h439 unsigned writemask)
446 nir_intrinsic_set_write_mask(store, writemask);
454 nir_ssa_def *value, unsigned writemask)
462 store->const_index[0] = writemask & ((1 << num_components) - 1);
438 nir_store_var(nir_builder *build, nir_variable *var, nir_ssa_def *value, unsigned writemask) argument
453 nir_store_deref_var(nir_builder *build, nir_deref_var *deref, nir_ssa_def *value, unsigned writemask) argument
/external/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_bld_depth.c269 if (stencil[0].writemask != 0xff ||
270 (stencil[1].enabled && front_facing != NULL && stencil[1].writemask != 0xff)) {
271 /* mask &= stencil[0].writemask */
272 LLVMValueRef writemask = lp_build_const_int_vec(bld->gallivm, bld->type, local
273 stencil[0].writemask);
274 if (stencil[1].enabled && stencil[1].writemask != stencil[0].writemask && front_facing != NULL) {
276 stencil[1].writemask);
277 writemask = lp_build_select(bld, front_facing, writemask, back_writemas
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/external/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h600 // The writemask for AVX-512 instructions which is contained in EVEX.aaa
601 Reg writemask; member in struct:llvm::X86Disassembler::InternalInstruction

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