Searched refs:Register (Results 151 - 175 of 805) sorted by relevance

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/external/tensorflow/tensorflow/core/util/
H A Dtensor_slice_set_test.cc54 TF_CHECK_OK(tss.Register(slice_1, "", src_1));
63 TF_CHECK_OK(tss.Register(slice_2, "", src_2));
72 TF_CHECK_OK(tss.Register(slice_3, "", src_3));
153 TF_CHECK_OK(tss.Register(slice_1, "slice_1", nullptr));
161 TF_CHECK_OK(tss.Register(slice_2, "slice_2", nullptr));
169 TF_CHECK_OK(tss.Register(slice_3, "slice_3", nullptr));
245 TF_CHECK_OK(slice_set.Register(part, part.DebugString(), nullptr));
/external/vixl/test/aarch64/
H A Dtest-utils-aarch64.h80 // Register accessors.
199 bool Equal32(uint32_t expected, const RegisterDump* core, const Register& reg);
200 bool Equal64(uint64_t expected, const RegisterDump* core, const Register& reg);
212 bool Equal64(const Register& reg0,
214 const Register& reg1);
234 RegList PopulateRegisterArray(Register* w,
235 Register* x,
236 Register* r,
/external/v8/src/crankshaft/mips64/
H A Dlithium-codegen-mips64.cc382 Register LCodeGen::ToRegister(int index) const {
383 return Register::from_code(index);
392 Register LCodeGen::ToRegister(LOperand* op) const {
398 Register LCodeGen::EmitLoadRegister(LOperand* op, Register scratch) {
647 Register reg = ToRegister(op);
752 environment->Register(deoptimization_index,
762 Register src1, const Operand& src2) {
775 Register scratch = scratch0();
827 DeoptimizeReason deopt_reason, Register src
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/external/v8/src/crankshaft/ia32/
H A Dlithium-codegen-ia32.h57 Register ToRegister(LOperand* op) const;
98 void DoDeferredInstanceMigration(LCheckMaps* instr, Register object);
100 Register object,
101 Register index);
125 Register input,
126 Register temporary,
127 Register temporary2);
192 void PrepareForTailCall(const ParameterCount& actual, Register scratch1,
193 Register scratch2, Register scratch
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/external/v8/src/crankshaft/mips/
H A Dlithium-codegen-mips.cc334 Register entry_offset = t9;
399 Register LCodeGen::ToRegister(int index) const {
400 return Register::from_code(index);
409 Register LCodeGen::ToRegister(LOperand* op) const {
415 Register LCodeGen::EmitLoadRegister(LOperand* op, Register scratch) {
659 Register reg = ToRegister(op);
764 environment->Register(deoptimization_index,
774 Register src1, const Operand& src2) {
787 Register scratc
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/external/v8/src/crankshaft/ppc/
H A Dlithium-codegen-ppc.cc328 Register entry_offset = scratch0();
392 Register LCodeGen::ToRegister(int code) const {
393 return Register::from_code(code);
402 Register LCodeGen::ToRegister(LOperand* op) const {
408 Register LCodeGen::EmitLoadRegister(LOperand* op, Register scratch) {
437 Register dst) {
626 Register reg = ToRegister(op);
731 environment->Register(deoptimization_index, translation.index(),
754 Register scratc
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/external/vixl/src/aarch64/
H A Dassembler-aarch64.cc180 void Assembler::br(const Register& xn) {
186 void Assembler::blr(const Register& xn) {
192 void Assembler::ret(const Register& xn) {
230 void Assembler::cbz(const Register& rt, int64_t imm19) {
235 void Assembler::cbz(const Register& rt, Label* label) {
242 void Assembler::cbnz(const Register& rt, int64_t imm19) {
247 void Assembler::cbnz(const Register& rt, Label* label) {
351 void Assembler::tbz(const Register& rt, unsigned bit_pos, int64_t imm14) {
357 void Assembler::tbz(const Register& rt, unsigned bit_pos, Label* label) {
364 void Assembler::tbnz(const Register
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H A Doperands-aarch64.h41 // Some CPURegister methods can return Register or VRegister types, so we need
43 class Register;
210 const Register& W() const;
211 const Register& X() const;
237 class Register : public CPURegister {
239 Register() : CPURegister() {}
240 explicit Register(const CPURegister& other)
244 Register(unsigned code, unsigned size) : CPURegister(code, size, kRegister) {}
251 static const Register& GetWRegFromCode(unsigned code);
253 static const Register
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/external/v8/src/ic/arm/
H A Dhandler-compiler-arm.cc22 MacroAssembler* masm, Handle<Map> map, Register receiver, Register holder,
23 int accessor_index, int expected_arguments, Register scratch) {
65 MacroAssembler* masm, Handle<Map> map, Register receiver, Register holder,
66 int accessor_index, int expected_arguments, Register scratch) {
111 void PropertyHandlerCompiler::PushVectorAndSlot(Register vector,
112 Register slot) {
125 void PropertyHandlerCompiler::PopVectorAndSlot(Register vector, Register slo
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/external/v8/src/ic/mips/
H A Dhandler-compiler-mips.cc22 MacroAssembler* masm, Handle<Map> map, Register receiver, Register holder,
23 int accessor_index, int expected_arguments, Register scratch) {
65 MacroAssembler* masm, Handle<Map> map, Register receiver, Register holder,
66 int accessor_index, int expected_arguments, Register scratch) {
107 void PropertyHandlerCompiler::PushVectorAndSlot(Register vector,
108 Register slot) {
120 void PropertyHandlerCompiler::PopVectorAndSlot(Register vector, Register slo
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/external/v8/src/ic/mips64/
H A Dhandler-compiler-mips64.cc22 MacroAssembler* masm, Handle<Map> map, Register receiver, Register holder,
23 int accessor_index, int expected_arguments, Register scratch) {
65 MacroAssembler* masm, Handle<Map> map, Register receiver, Register holder,
66 int accessor_index, int expected_arguments, Register scratch) {
107 void PropertyHandlerCompiler::PushVectorAndSlot(Register vector,
108 Register slot) {
120 void PropertyHandlerCompiler::PopVectorAndSlot(Register vector, Register slo
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/external/v8/src/ic/ppc/
H A Dhandler-compiler-ppc.cc22 MacroAssembler* masm, Handle<Map> map, Register receiver, Register holder,
23 int accessor_index, int expected_arguments, Register scratch) {
65 MacroAssembler* masm, Handle<Map> map, Register receiver, Register holder,
66 int accessor_index, int expected_arguments, Register scratch) {
108 void PropertyHandlerCompiler::PushVectorAndSlot(Register vector,
109 Register slot) {
121 void PropertyHandlerCompiler::PopVectorAndSlot(Register vector, Register slo
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/external/v8/src/crankshaft/s390/
H A Dlithium-codegen-s390.cc316 Register entry_offset = scratch0();
379 Register LCodeGen::ToRegister(int code) const {
380 return Register::from_code(code);
387 Register LCodeGen::ToRegister(LOperand* op) const {
392 Register LCodeGen::EmitLoadRegister(LOperand* op, Register scratch) {
420 Register dst) {
595 Register reg = ToRegister(op);
694 environment->Register(deoptimization_index, translation.index(),
716 Register scratc
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/external/llvm/include/llvm/MC/
H A DMCDwarf.h348 unsigned Register; member in class:llvm::MCCFIInstruction
356 : Operation(Op), Label(L), Register(R), Offset(O),
362 : Operation(Op), Label(L), Register(R1), Register2(R2) {
368 /// Register and add Offset to it.
369 static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, argument
371 return MCCFIInstruction(OpDefCfa, L, Register, -Offset, "");
375 /// on Register will be used instead of the old one. Offset remains the same.
376 static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register) { argument
377 return MCCFIInstruction(OpDefCfaRegister, L, Register, 0, "");
380 /// \brief .cfi_def_cfa_offset modifies a rule for computing CFA. Register
396 createOffset(MCSymbol *L, unsigned Register, int Offset) argument
404 createRelOffset(MCSymbol *L, unsigned Register, int Offset) argument
424 createRestore(MCSymbol *L, unsigned Register) argument
430 createUndefined(MCSymbol *L, unsigned Register) argument
436 createSameValue(MCSymbol *L, unsigned Register) argument
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/external/v8/src/crankshaft/x64/
H A Dlithium-codegen-x64.h56 Register ToRegister(LOperand* op) const;
96 void DoDeferredInstanceMigration(LCheckMaps* instr, Register object);
98 Register object,
99 Register index);
123 Register input,
124 Register temporary,
125 Register scratch);
193 void PrepareForTailCall(const ParameterCount& actual, Register scratch1,
194 Register scratch2, Register scratch
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/external/swiftshader/third_party/LLVM/lib/MC/
H A DMCAsmStreamer.cpp61 void EmitRegisterName(int64_t Register);
208 virtual void EmitCFIDefCfa(int64_t Register, int64_t Offset);
210 virtual void EmitCFIDefCfaRegister(int64_t Register);
211 virtual void EmitCFIOffset(int64_t Register, int64_t Offset);
216 virtual void EmitCFISameValue(int64_t Register);
217 virtual void EmitCFIRelOffset(int64_t Register, int64_t Offset);
227 virtual void EmitWin64EHPushReg(unsigned Register);
228 virtual void EmitWin64EHSetFrame(unsigned Register, unsigned Offset);
230 virtual void EmitWin64EHSaveReg(unsigned Register, unsigned Offset);
231 virtual void EmitWin64EHSaveXMM(unsigned Register, unsigne
839 EmitRegisterName(int64_t Register) argument
845 OS << Register; local
849 EmitCFIDefCfa(int64_t Register, int64_t Offset) argument
871 EmitCFIDefCfaRegister(int64_t Register) argument
882 EmitCFIOffset(int64_t Register, int64_t Offset) argument
935 EmitCFISameValue(int64_t Register) argument
946 EmitCFIRelOffset(int64_t Register, int64_t Offset) argument
1038 EmitWin64EHPushReg(unsigned Register) argument
1041 OS << "\\t.seh_pushreg " << Register; local
1045 EmitWin64EHSetFrame(unsigned Register, unsigned Offset) argument
1059 EmitWin64EHSaveReg(unsigned Register, unsigned Offset) argument
1066 EmitWin64EHSaveXMM(unsigned Register, unsigned Offset) argument
[all...]
/external/v8/src/ic/arm64/
H A Dhandler-compiler-arm64.cc20 void PropertyHandlerCompiler::PushVectorAndSlot(Register vector,
21 Register slot) {
34 void PropertyHandlerCompiler::PopVectorAndSlot(Register vector, Register slot) {
48 MacroAssembler* masm, Label* miss_label, Register receiver,
49 Handle<Name> name, Register scratch0, Register scratch1) {
62 Register map = scratch1;
74 Register properties = scratch0;
91 Register scratc
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/external/v8/src/ic/s390/
H A Dhandler-compiler-s390.cc21 MacroAssembler* masm, Handle<Map> map, Register receiver, Register holder,
22 int accessor_index, int expected_arguments, Register scratch) {
63 MacroAssembler* masm, Handle<Map> map, Register receiver, Register holder,
64 int accessor_index, int expected_arguments, Register scratch) {
105 void PropertyHandlerCompiler::PushVectorAndSlot(Register vector,
106 Register slot) {
117 void PropertyHandlerCompiler::PopVectorAndSlot(Register vector, Register slo
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/external/capstone/arch/X86/
H A DX86GenRegisterInfo.inc3 |*Target Register Enum Values *|
254 // Register classes
637 // GR8 Register Class...
647 // GR8_NOREX Register Class...
657 // GR8_ABCD_H Register Class...
667 // GR8_ABCD_L Register Class...
677 // GR16 Register Class...
687 // GR16_NOREX Register Class...
697 // VK1 Register Class...
707 // VK16 Register Clas
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/external/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_lowering.c71 dst->Register.WriteMask &= wrmask;
72 assert(dst->Register.WriteMask);
90 get_swiz(swiz, &orig_src->Register);
92 src->Register.SwizzleX = swiz[sx];
93 src->Register.SwizzleY = swiz[sy];
94 src->Register.SwizzleZ = swiz[sz];
95 src->Register.SwizzleW = swiz[sw];
115 if ((dst->Register.File == src->Register.File) &&
116 (dst->Register
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/external/v8/src/crankshaft/arm/
H A Dlithium-codegen-arm.cc315 Register entry_offset = scratch0();
384 Register LCodeGen::ToRegister(int code) const {
385 return Register::from_code(code);
394 Register LCodeGen::ToRegister(LOperand* op) const {
400 Register LCodeGen::EmitLoadRegister(LOperand* op, Register scratch) {
643 Register reg = ToRegister(op);
770 environment->Register(deoptimization_index,
792 Register scratch = scratch0();
966 Register dividen
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/external/v8/src/x64/
H A Dassembler-x64.cc158 Operand::Operand(Register base, int32_t disp) : rex_(0) {
177 Operand::Operand(Register base,
178 Register index,
198 Operand::Operand(Register index,
263 bool Operand::AddressUsesRegister(Register reg) const {
493 Register reg,
504 Register reg,
505 Register rm_reg,
522 void Assembler::arithmetic_op_16(byte opcode, Register reg, Register rm_re
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/external/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dfd2_compiler.c437 add_dst_reg(ctx, alu, &inst->Dst[0].Register);
438 add_src_reg(ctx, alu, &inst->Src[0].Register);
439 add_src_reg(ctx, alu, &inst->Src[0].Register);
450 add_dst_reg(ctx, alu, &inst->Dst[0].Register);
451 add_src_reg(ctx, alu, &inst->Src[0].Register);
452 add_src_reg(ctx, alu, &inst->Src[1].Register);
463 add_dst_reg(ctx, alu, &inst->Dst[0].Register);
468 add_src_reg(ctx, alu, &inst->Src[2].Register);
469 add_src_reg(ctx, alu, &inst->Src[0].Register);
470 add_src_reg(ctx, alu, &inst->Src[1].Register);
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/external/v8/src/ic/ia32/
H A Dhandler-compiler-ia32.cc22 MacroAssembler* masm, Handle<Map> map, Register receiver, Register holder,
23 int accessor_index, int expected_arguments, Register scratch) {
59 void PropertyHandlerCompiler::PushVectorAndSlot(Register vector,
60 Register slot) {
73 void PropertyHandlerCompiler::PopVectorAndSlot(Register vector, Register slot) {
87 MacroAssembler* masm, Label* miss_label, Register receiver,
88 Handle<Name> name, Register scratch0, Register scratch
[all...]
/external/v8/src/ic/x87/
H A Dhandler-compiler-x87.cc22 MacroAssembler* masm, Handle<Map> map, Register receiver, Register holder,
23 int accessor_index, int expected_arguments, Register scratch) {
59 void PropertyHandlerCompiler::PushVectorAndSlot(Register vector,
60 Register slot) {
73 void PropertyHandlerCompiler::PopVectorAndSlot(Register vector, Register slot) {
87 MacroAssembler* masm, Label* miss_label, Register receiver,
88 Handle<Name> name, Register scratch0, Register scratch
[all...]

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