Searched refs:Select (Results 226 - 250 of 263) sorted by relevance

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/external/llvm/bindings/ocaml/llvm/
H A D	llvm.ml	202 | Select Constructor in type:Opcode/t
/external/llvm/lib/Bitcode/Writer/
H A D	BitcodeWriter.cpp	2165 case Instruction::Select: 2348 case Instruction::Select:
/external/llvm/lib/Target/AArch64/
H A D	AArch64ISelDAGToDAG.cpp	60 void Select(SDNode *Node) override; 250 /// SelectArithImmed - Select an immediate value that can be represented as 338 /// SelectShiftedRegister - Select a "shifted register" operand. If the value 563 /// SelectArithExtendedRegister - Select a "extended register" operand. This 624 /// SelectAddrModeIndexed7S - Select a "register plus scaled signed 7-bit 669 /// SelectAddrModeIndexed - Select a "register plus scaled unsigned 12-bit 732 /// SelectAddrModeUnscaled - Select a "register plus unscaled signed 9-bit 2555 void AArch64DAGToDAGISel::Select(SDNode *Node) { function in class:AArch64DAGToDAGISel 2629 // Bail and use the default Select() for non-zero lanes. 2633 // bail and use the default Select(), a [all...]
H A D	AArch64FastISel.cpp	4975 case Instruction::Select:
/external/llvm/lib/Target/ARM/
H A D	ARMISelDAGToDAG.cpp	85 void Select(SDNode *N) override; 200 /// SelectVLD - Select NEON load intrinsics. NumVecs should be 208 /// SelectVST - Select NEON store intrinsics. NumVecs should 216 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should 223 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs 229 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2, 237 // Select special operations if node forms integer ABS pattern 2664 void ARMDAGToDAGISel::Select(SDNode *N) { function in class:ARMDAGToDAGISel 2692 // Select special operations if XOR node forms integer ABS pattern 2860 // Select i [all...]
H A D	ARMFastISel.cpp	2852 case Instruction::Select:
/external/llvm/lib/Target/NVPTX/
H A D	NVPTXISelLowering.cpp	1865 SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2); 1866 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select);
H A D	NVPTXISelDAGToDAG.cpp	106 /// Select - Select instructions not customized! Used for 108 void NVPTXDAGToDAGISel::Select(SDNode *N) { function in class:NVPTXDAGToDAGISel
/external/owasp/sanitizer/tools/findbugs/lib/
H A D	bcel.jar	META-INF/ META-INF/MANIFEST.MF org/ org/apache/ org/apache/bcel/ org/apache/bcel/classfile/ ...
/external/guice/extensions/struts2/lib/
H A D	struts2-core-2.2.1.jar	META-INF/ META-INF/MANIFEST.MF org/ org/apache/ org/apache/struts2/ org/apache/struts2/dispatcher/ ...
/external/llvm/lib/Transforms/Vectorize/
H A D	LoopVectorize.cpp	4002 // Select between the current value and the previous incoming edge 4113 case Instruction::Select: { 5233 // Select the largest VF which doesn't require more registers than existing 5897 case Instruction::Select: { 6485 // Select the optimal vectorization factor. 6489 // Select the interleave count.
H A D	BBVectorize.cpp	584 case Instruction::Select:
/external/llvm/lib/ExecutionEngine/Interpreter/
H A D	Execution.cpp	2010 case Instruction::Select:
/external/llvm/lib/Target/X86/
H A D	X86FastISel.cpp	53 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 1090 /// X86SelectStore - Select and emit code to implement store instructions. 1133 /// X86SelectRet - Select and emit code to implement ret instructions. 1280 /// X86SelectLoad - Select and emit code to implement load instructions. 2280 // Select integer to float/double conversion. 3427 case Instruction::Select: 3451 // Select SSE2/AVX bitcasts between 128/256 bit vector types.
/external/pdfium/xfa/fxfa/
H A D	cxfa_widgetacc.cpp	1803 XFA_AttributeEnum::Select;
/external/swiftshader/third_party/LLVM/lib/Analysis/
H A D	InstructionSimplify.cpp	2495 case Instruction::Select:
H A D	ScalarEvolution.cpp	3816 case Instruction::Select:
/external/swiftshader/third_party/LLVM/lib/AsmParser/
H A D	LLParser.cpp	2310 } else if (Opc == Instruction::Select) {
/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/
H A D	ObjCARC.cpp	318 case Instruction::Select: case Instruction::PHI: 956 // Check both arms of the Select node individually. 1063 // Special handling for PHI and Select.
/external/v8/src/builtins/
H A D	builtins-array.cc	598 // Select by ElementsKind 1720 index_var.Bind(Select( function
/external/v8/src/compiler/
H A D	ast-graph-builder.cc	2166 Node* value = NewNode(common()->Select(MachineRepresentation::kTagged), input,
/external/llvm/lib/Analysis/
H A D	InstructionSimplify.cpp	4185 case Instruction::Select:
/external/llvm/lib/Transforms/InstCombine/
H A D	InstCombineCompares.cpp	3035 /// \param SI Select instruction 3657 case Instruction::Select: {
/external/robolectric/v1/lib/main/
H A D	h2-1.2.147.jar	META-INF/MANIFEST.MF META-INF/services/java.sql.Driver org/h2/api/AggregateFunction ...
/external/llvm/lib/AsmParser/
H A D	LLParser.cpp	3201 } else if (Opc == Instruction::Select) {

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Indexes created Sun Aug 12 02:23:12 CEST 2018