| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| H A D | VirtRegMap.cpp | 183 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, argument
194 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
197 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) { argument
199 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
281 unsigned VirtReg = MO.getReg(); local
282 unsigned PhysReg = getPhys(VirtReg);
283 assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg");
|
| H A D | InlineSpiller.cpp | 834 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, argument
837 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
843 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
859 markValueUsed(&VirtReg, ParentVNI);
864 // If the instruction also writes VirtReg.reg, it had better not require the
868 tie(Reads, Writes) = MI->readsWritesVirtualRegister(VirtReg.reg, &Ops);
873 markValueUsed(&VirtReg, ParentVNI);
902 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
|
| H A D | PrologEpilogInserter.cpp | 822 unsigned VirtReg = 0; local
842 if (Reg != VirtReg) {
848 VirtReg = Reg;
|
| /external/llvm/lib/CodeGen/ |
| H A D | LiveDebugVariables.cpp | 310 /// lookupVirtReg - Find the EC leader for VirtReg or null.
311 UserValue *lookupVirtReg(unsigned VirtReg);
349 void mapVirtReg(unsigned VirtReg, UserValue *EC);
479 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { argument
480 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs");
481 UserValue *&Leader = virtRegToEqClass[VirtReg];
485 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { argument
486 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
923 unsigned VirtReg = Loc.getReg(); local
924 if (VRM.isAssignedReg(VirtReg)
[all...] |
| H A D | TargetRegisterInfo.cpp | 330 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
337 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
349 // Check that Phys is a valid hint in VirtReg's register class.
355 // from VirtReg's register class if they aren't in the allocation order. The
|
| H A D | MachineBasicBlock.cpp | 381 unsigned VirtReg = I->getOperand(0).getReg(); local
382 if (!MRI.constrainRegClass(VirtReg, RC))
384 return VirtReg;
388 unsigned VirtReg = MRI.createVirtualRegister(RC); local
389 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
393 return VirtReg;
|
| H A D | InlineSpiller.cpp | 501 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { argument
506 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
512 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
518 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
534 markValueUsed(&VirtReg, ParentVNI);
539 // If the instruction also writes VirtReg.reg, it had better not require the
542 markValueUsed(&VirtReg, ParentVNI);
569 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
1447 /// For VirtReg clone, the \p New register should have the same physreg or
|
| H A D | PHIElimination.cpp | 200 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
202 static bool isImplicitlyDefined(unsigned VirtReg, argument
204 for (MachineInstr &DI : MRI->def_instructions(VirtReg))
|
| H A D | MachineTraceMetrics.cpp | 614 DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp)
616 assert(TargetRegisterInfo::isVirtualRegister(VirtReg));
617 MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg);
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | ScheduleDAGInstrs.h | 36 unsigned VirtReg; member in struct:llvm::VReg2SUnit
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
44 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
| H A D | RegisterPressure.h | 522 bool hasUntiedDef(unsigned VirtReg) const {
523 return UntiedDefs.count(VirtReg);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 134 void getRegAllocationHints(unsigned VirtReg,
|
| H A D | ARMBaseRegisterInfo.cpp | 255 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, argument
262 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
273 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
|
| /external/llvm/include/llvm/Target/ |
| H A D | TargetRegisterInfo.h | 747 /// VirtReg. These registers are effectively moved to the front of the
750 /// The Order argument is the allocation order for VirtReg's register class
758 /// order for VirtReg. There may be target-independent hints.
759 virtual void getRegAllocationHints(unsigned VirtReg,
|