Searched refs:inst (Results 176 - 200 of 552) sorted by relevance

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/external/llvm/bindings/python/llvm/tests/
H A Dtest_core.py125 for inst in bb:
126 self.assertEqual(inst.name, inst_list[i][0])
127 self.assertEqual(inst.opcode, inst_list[i][1])
128 for op in range(len(inst)):
129 o = inst.get_operand(op)
132 inst.dump()
136 for inst in reversed(bb):
138 self.assertEqual(inst.name, inst_list[i][0])
139 self.assertEqual(inst.opcode, inst_list[i][1])
140 inst
[all...]
/external/swiftshader/third_party/subzero/crosstest/
H A Dtest_bitmanip_main.cpp56 #define X(inst) \
57 { STR(inst), test_##inst, Subzero_::test_##inst } \
58 , {STR(inst) "_alloca", test_alloca_##inst, Subzero_::test_alloca_##inst}, \
59 {STR(inst) "_const", test_const_##inst, Subzero_::test_const_##inst},
[all...]
H A Dtest_arith_main.cpp68 #define X(inst, op, isdiv, isshift) \
69 { STR(inst), test##inst, Subzero_::test##inst, NULL, NULL, isdiv } \
73 #define X(inst, op, isdiv, isshift) \
74 { STR(inst), NULL, NULL, test##inst, Subzero_::test##inst, isdiv } \
189 #define X(inst, op, isdiv, isshift) \
190 { STR(inst), tes
[all...]
H A Dtest_sync_atomic_main.cpp67 #define X(inst) \
68 { STR(inst), test_##inst, Subzero_::test_##inst } \
69 , {STR(inst) "_alloca", test_alloca_##inst, Subzero_::test_alloca_##inst}, \
70 {STR(inst) "_const", test_const_##inst, Subzero_::test_const_##inst},
[all...]
/external/vulkan-validation-layers/loader/
H A Dextension_manual.c38 VkResult setupLoaderTermPhysDevGroups(struct loader_instance *inst);
48 struct loader_instance *inst = NULL; local
52 inst = loader_get_instance(instance);
53 if (NULL == inst) {
59 loader_log(inst, VK_DEBUG_REPORT_ERROR_BIT_EXT, 0,
72 count = inst->phys_dev_group_count_tramp;
76 if (inst->phys_dev_group_count_tramp > *pPhysicalDeviceGroupCount) {
77 loader_log(inst, VK_DEBUG_REPORT_INFORMATION_BIT_EXT, 0,
80 inst->phys_dev_group_count_tramp, *pPhysicalDeviceGroupCount);
85 memcpy(&pPhysicalDeviceGroupProperties[i], inst
101 struct loader_instance *inst = (struct loader_instance *)instance; local
938 struct loader_instance *inst; local
1117 setupLoaderTermPhysDevGroups(struct loader_instance *inst) argument
[all...]
/external/mesa3d/src/gallium/drivers/ilo/shader/
H A Dilo_shader_fs.c266 struct toy_inst *inst; local
274 inst = tc_MOV(tc, offset, real_src[0]);
275 inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
277 switch (inst->exec_size) {
300 inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, GEN6_SFID_SAMPLER);
301 inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
350 struct toy_inst *inst; local
359 inst = tc_MOV(tc, header, r0);
360 inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
363 inst
397 struct toy_inst *inst; local
479 fs_lower_opcode_tgsi_direct(struct fs_compile_context *fcc, struct toy_inst *inst) argument
517 fs_lower_opcode_tgsi_indirect(struct fs_compile_context *fcc, struct toy_inst *inst) argument
717 fs_prepare_tgsi_sampling(struct fs_compile_context *fcc, const struct toy_inst *inst, int base_mrf, const uint32_t *saturate_coords, unsigned *ret_sampler_index) argument
1097 fs_lower_opcode_tgsi_sampling(struct fs_compile_context *fcc, struct toy_inst *inst) argument
1169 fs_lower_opcode_derivative(struct toy_compiler *tc, struct toy_inst *inst) argument
1223 fs_lower_opcode_fb_write(struct toy_compiler *tc, struct toy_inst *inst) argument
1231 fs_lower_opcode_kil(struct toy_compiler *tc, struct toy_inst *inst) argument
1284 struct toy_inst *inst; local
1474 struct toy_inst *inst; local
1534 struct toy_inst *inst; local
[all...]
H A Dilo_shader_vs.c115 struct toy_inst *inst; local
122 inst = tc_MOV(tc, header, r0);
123 inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
230 struct toy_inst *inst)
235 assert(inst->src[0].file == TOY_FILE_IMM);
236 dim = inst->src[0].val32;
238 assert(inst->src[1].file == TOY_FILE_IMM);
239 idx = inst->src[1].val32;
241 switch (inst->opcode) {
243 vs_lower_opcode_tgsi_in(vcc, inst
229 vs_lower_opcode_tgsi_direct(struct vs_compile_context *vcc, struct toy_inst *inst) argument
267 vs_lower_opcode_tgsi_indirect(struct vs_compile_context *vcc, struct toy_inst *inst) argument
390 vs_prepare_tgsi_sampling(struct vs_compile_context *vcc, const struct toy_inst *inst, int base_mrf, unsigned *ret_sampler_index) argument
568 vs_lower_opcode_tgsi_sampling(struct vs_compile_context *vcc, struct toy_inst *inst) argument
651 vs_lower_opcode_urb_write(struct toy_compiler *tc, struct toy_inst *inst) argument
661 struct toy_inst *inst; local
914 struct toy_inst *inst; local
[all...]
H A Dtoy_compiler.c427 tc_dump_inst(struct toy_compiler *tc, const struct toy_inst *inst) argument
432 name = get_opcode_name(inst->opcode);
436 if (inst->opcode == GEN6_OPCODE_NOP) {
441 if (inst->saturate)
444 name = get_cond_modifier_name(inst->opcode, inst->cond_modifier);
450 tc_dump_dst(tc, inst->dst);
452 for (i = 0; i < ARRAY_SIZE(inst->src); i++) {
453 if (tsrc_is_null(inst->src[i]))
457 tc_dump_src(tc, inst
469 struct toy_inst *inst; local
491 struct toy_inst *inst, *next; local
[all...]
/external/mesa3d/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c230 const struct tgsi_full_instruction *inst);
3463 const struct tgsi_full_instruction *inst)
3465 unsigned index = inst->Dst[0].Register.Index;
3480 if (inst->Instruction.Opcode == TGSI_OPCODE_ARL)
3485 emit_instruction_op1(emit, opcode, &dst, &inst->Src[0], FALSE);
3496 const struct tgsi_full_instruction *inst)
3498 unsigned label = inst->Label.Label;
3517 const struct tgsi_full_instruction *inst)
3527 struct tgsi_full_src_register neg_src = negate_src(&inst->Src[0]);
3528 emit_instruction_op2(emit, VGPU10_OPCODE_IMAX, &inst
3462 emit_arl_uarl(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3495 emit_cal(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3516 emit_iabs(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3539 emit_cmp(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3572 emit_dp2a(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3621 emit_dph(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3655 emit_dst(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3731 emit_endprim(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3750 emit_ex2(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3776 emit_exp(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3859 emit_if(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3891 emit_kill_if(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3944 emit_kill(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3963 emit_lg2(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
3989 emit_lit(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4130 emit_log(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4213 emit_lrp(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4246 emit_pow(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4288 emit_rcp(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4320 emit_rsq(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4358 emit_scs(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4394 emit_seq(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4427 emit_sge(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4460 emit_sgt(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4493 emit_sincos(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4534 emit_sle(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4567 emit_slt(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4600 emit_sne(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4633 emit_ssg(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4680 emit_issg(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
4801 get_texel_offsets(const struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst, int offsets[3]) argument
4915 begin_tex_swizzle(struct svga_shader_emitter_v10 *emit, unsigned unit, const struct tgsi_full_instruction *inst, boolean shadow_compare, struct tex_swizzle_info *swz) argument
5081 emit_sample(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
5124 is_valid_tex_instruction(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
5156 emit_tex(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
5206 emit_txp(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
5265 emit_xpd(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
5376 emit_txd(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
5416 emit_txf(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
5467 emit_txl_txb(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
5524 emit_txq(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
5559 emit_simple(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
5586 emit_mov(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
5609 emit_simple_1dst(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst, unsigned dst_count, unsigned dst_index) argument
5643 emit_vgpu10_instruction(struct svga_shader_emitter_v10 *emit, unsigned inst_number, const struct tgsi_full_instruction *inst) argument
6025 emit_vertex(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst) argument
[all...]
H A Dsvga_tgsi_emit.h194 SVGA3dShaderInstToken inst; local
196 inst.value = 0;
197 inst.op = opcode;
199 return inst;
210 SVGA3dShaderInstToken inst; local
212 inst.value = 0;
213 inst.op = opcode;
214 inst.predicated = 1;
216 return inst;
227 SVGA3dShaderInstToken inst; local
[all...]
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_fs_builder.h68 * before instruction \p inst in basic block \p block. The default
72 fs_builder(backend_shader *shader, bblock_t *block, fs_inst *inst) : argument
73 shader(shader), block(block), cursor(inst),
74 _dispatch_width(inst->exec_size),
75 _group(inst->group),
76 force_writemask_all(inst->force_writemask_all)
78 annotation.str = inst->annotation;
79 annotation.ir = inst->ir;
254 emit(const instruction &inst) const
256 return emit(new(shader->mem_ctx) instruction(inst));
570 instruction *inst = emit(SHADER_OPCODE_LOAD_PAYLOAD, dst, src, sources); local
[all...]
H A Dbrw_vec4_gs_visitor.cpp159 vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, brw_imm_ud(0u)); local
160 inst->force_writemask_all = true;
167 inst = emit(MOV(dst_reg(this->vertex_count), brw_imm_ud(0u)));
168 inst->force_writemask_all = true;
182 inst = emit(MOV(dst_reg(this->control_data_bits), brw_imm_ud(0u)));
183 inst->force_writemask_all = true;
228 vec4_instruction *inst = emit(MOV(mrf_reg, r0)); local
229 inst->force_writemask_all = true;
234 inst = emit(GS_OPCODE_THREAD_END);
235 inst
254 vec4_instruction *inst = emit(MOV(mrf_reg, r0)); local
270 vec4_instruction *inst = emit(GS_OPCODE_URB_WRITE); local
351 vec4_instruction *inst = emit(MOV(mrf_reg, r0)); local
487 vec4_instruction *inst = local
[all...]
H A Dgen6_gs_visitor.cpp74 vec4_instruction *inst = emit(MOV(dst_reg(MRF, 1), local
77 inst->force_writemask_all = true;
169 vec4_instruction *inst = emit(MOV(dst, src_reg(tmp))); local
170 inst->force_writemask_all = true;
225 vec4_instruction *inst = emit(CMP(dst_null_ud(), local
228 inst->predicate = BRW_PREDICATE_NORMAL;
293 vec4_instruction *inst = NULL; local
297 inst = emit(GS_OPCODE_URB_WRITE);
298 inst->urb_write_flags = BRW_URB_WRITE_NO_FLAGS;
308 inst
358 vec4_instruction *inst; local
417 vec4_instruction *inst = emit(MOV(reg, data)); local
479 vec4_instruction *inst = emit(GS_OPCODE_THREAD_END); local
614 vec4_instruction *inst = emit(MOV(dst_reg(destination_indices), local
668 vec4_instruction *inst = emit(GS_OPCODE_SVB_SET_DST_INDEX, local
[all...]
H A Dbrw_inst.h47 static inline uint64_t brw_inst_bits(const brw_inst *inst,
49 static inline void brw_inst_set_bits(brw_inst *inst,
56 brw_inst *inst, uint64_t v) \
60 brw_inst_set_bits(inst, high, low, v); \
64 const brw_inst *inst) \
68 return brw_inst_bits(inst, high, low); \
98 brw_inst *inst, uint64_t value) \
101 brw_inst_set_bits(inst, high, low, value); \
104 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
107 return brw_inst_bits(inst, hig
251 brw_inst_set_uip(const struct gen_device_info *devinfo, brw_inst *inst, int32_t value) argument
266 brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst) argument
278 brw_inst_set_jip(const struct gen_device_info *devinfo, brw_inst *inst, int32_t value) argument
293 brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst) argument
704 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low) argument
724 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value) argument
759 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low) argument
772 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low, uint64_t value) argument
[all...]
H A Dbrw_eu_emit.c145 brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest) argument
156 brw_inst_set_dst_reg_file(devinfo, inst, dest.file);
157 brw_inst_set_dst_reg_type(devinfo, inst,
160 brw_inst_set_dst_address_mode(devinfo, inst, dest.address_mode);
163 brw_inst_set_dst_da_reg_nr(devinfo, inst, dest.nr);
165 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
166 brw_inst_set_dst_da1_subreg_nr(devinfo, inst, dest.subnr);
169 brw_inst_set_dst_hstride(devinfo, inst, dest.hstride);
171 brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16);
172 brw_inst_set_da16_writemask(devinfo, inst, des
225 validate_reg(const struct gen_device_info *devinfo, brw_inst *inst, struct brw_reg reg) argument
321 brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) argument
474 brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) argument
563 brw_set_message_descriptor(struct brw_codegen *p, brw_inst *inst, enum brw_message_target sfid, unsigned msg_length, unsigned response_length, bool header_present, bool end_of_thread) argument
596 brw_set_math_message( struct brw_codegen *p, brw_inst *inst, unsigned function, unsigned integer_type, bool low_precision, unsigned dataType ) argument
759 brw_set_sampler_message(struct brw_codegen *p, brw_inst *inst, unsigned binding_table_index, unsigned sampler, unsigned msg_type, unsigned response_length, unsigned msg_length, unsigned header_present, unsigned simd_mode, unsigned return_format) argument
786 gen7_set_dp_scratch_message(struct brw_codegen *p, brw_inst *inst, bool write, bool dword, bool invalidate_after_read, unsigned num_regs, unsigned addr_offset, unsigned mlen, unsigned rlen, bool header_present) argument
873 brw_inst *inst = next_insn(p, opcode); local
1186 brw_inst *inst; local
1274 brw_inst *inst = brw_alu2(p, BRW_OPCODE_JMPI, ip, ip, index); local
1285 push_if_stack(struct brw_codegen *p, brw_inst *inst) argument
1305 push_loop_stack(struct brw_codegen *p, brw_inst *inst) argument
1790 brw_inst *inst; local
3348 brw_inst *inst; local
3459 brw_inst *inst; local
3586 struct brw_inst *inst; local
[all...]
H A Dbrw_vec4_tcs.cpp111 vec4_instruction *inst; local
160 inst = emit(TCS_OPCODE_THREAD_END);
161 inst->base_mrf = 14;
162 inst->mlen = 2;
173 vec4_instruction *inst; local
179 inst = emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
181 inst->force_writemask_all = true;
184 inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
185 inst->offset = base_offset;
186 inst
208 vec4_instruction *inst; local
239 vec4_instruction *inst; local
[all...]
H A Dbrw_fs_live_variables.cpp56 fs_live_variables::setup_one_read(struct block_data *bd, fs_inst *inst, argument
74 fs_live_variables::setup_one_write(struct block_data *bd, fs_inst *inst, argument
86 if (inst->dst.file == VGRF && !inst->is_partial_write()) {
113 foreach_inst_in_block(fs_inst, inst, block) {
115 for (unsigned int i = 0; i < inst->sources; i++) {
116 fs_reg reg = inst->src[i];
121 for (unsigned j = 0; j < regs_read(inst, i); j++) {
122 setup_one_read(bd, inst, ip, reg);
127 bd->flag_use[0] |= inst
78 assert(var < num_vars); start[var] = MIN2(start[var], ip); end[var] = MAX2(end[var], ip); if (inst->dst.file == VGRF && !inst->is_partial_write()) argument
[all...]
/external/webrtc/webrtc/modules/video_coding/codecs/vp8/
H A Dsimulcast_encoder_adapter.cc70 int VerifyCodec(const webrtc::VideoCodec* inst) {
71 if (inst == NULL) {
74 if (inst->maxFramerate < 1) {
78 if (inst->maxBitrate > 0 && inst->startBitrate > inst->maxBitrate) {
81 if (inst->width <= 1 || inst->height <= 1) {
84 if (inst->codecSpecific.VP8.feedbackModeOn &&
85 inst
164 InitEncode(const VideoCodec* inst, int number_of_cores, size_t max_payload_size) argument
438 PopulateStreamCodec( const webrtc::VideoCodec* inst, int stream_index, size_t total_number_of_streams, bool highest_resolution_stream, webrtc::VideoCodec* stream_codec, bool* send_stream) argument
[all...]
/external/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp59 void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const;
101 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
1196 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, argument
1200 if ((inst & V4_SL1_loadri_io_MASK) == V4_SL1_loadri_io_BITS)
1202 else if ((inst & V4_SL1_loadrub_io_MASK) == V4_SL1_loadrub_io_BITS)
1210 if ((inst & V4_SL2_deallocframe_MASK) == V4_SL2_deallocframe_BITS)
1212 else if ((inst & V4_SL2_jumpr31_MASK) == V4_SL2_jumpr31_BITS)
1214 else if ((inst & V4_SL2_jumpr31_f_MASK) == V4_SL2_jumpr31_f_BITS)
1216 else if ((inst & V4_SL2_jumpr31_fnew_MASK) == V4_SL2_jumpr31_fnew_BITS)
1218 else if ((inst
[all...]
/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dr3xx_fragprog.c57 struct rc_sub_instruction * inst = &rci->U.I; local
59 const struct rc_opcode_info *info = rc_get_opcode_info(inst->Opcode);
61 if (inst->DstReg.File != RC_FILE_OUTPUT || inst->DstReg.Index != c->OutputDepth)
64 if (inst->DstReg.WriteMask & RC_MASK_Z) {
65 inst->DstReg.WriteMask = RC_MASK_W;
67 inst->DstReg.WriteMask = 0;
76 inst->SrcReg[i] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[i]);
H A Dradeon_variable.c127 rc_error(var->C, "Rewrite of inst %u failed "
158 struct rc_instruction * inst; local
195 for (inst = var->Inst; inst != var->Readers[i].Inst;
196 inst = inst->Next) {
197 rc_opcode op = rc_get_flow_control_inst(inst);
200 rc_match_endloop(inst);
206 rc_match_bgnloop(inst);
315 struct rc_instruction * inst,
312 get_variable_pair_helper( struct rc_list ** variable_list, struct radeon_compiler * c, struct rc_instruction * inst, struct rc_pair_sub_instruction * sub_inst) argument
357 struct rc_instruction * inst; local
[all...]
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dr200_fragshader.c38 #define SET_INST(inst, type) afs_cmd[((inst<<2) + (type<<1) + 1)]
39 #define SET_INST_2(inst, type) afs_cmd[((inst<<2) + (type<<1) + 2)]
145 struct atifs_instruction *inst = &shader->Instructions[pass][pc]; local
155 if (inst->Opcode[optype]) {
156 switch (inst->Opcode[optype]) {
170 inst->SrcReg[optype][0], 1, &tfactor);
172 inst->SrcReg[optype][1], 2, &tfactor);
180 inst
[all...]
/external/python/cpython2/Lib/test/
H A Dpydocfodder.py196 def __call__(self, inst):
197 print 'Get called', self, inst
198 return inst.desc[self.attr]
202 def __call__(self, inst, val):
203 print 'Set called', self, inst, val
204 inst.desc[self.attr] = val
208 def __call__(self, inst):
209 print 'Del called', self, inst
210 del inst.desc[self.attr]
/external/python/cpython3/Lib/test/
H A Dpydocfodder.py196 def __call__(self, inst):
197 print('Get called', self, inst)
198 return inst.desc[self.attr]
202 def __call__(self, inst, val):
203 print('Set called', self, inst, val)
204 inst.desc[self.attr] = val
208 def __call__(self, inst):
209 print('Del called', self, inst)
210 del inst.desc[self.attr]
/external/mesa3d/src/mesa/state_tracker/
H A Dst_glsl_to_tgsi.cpp649 glsl_to_tgsi_instruction *inst = new(mem_ctx) glsl_to_tgsi_instruction(); local
684 /* inst->op has only 8 bits. */
687 inst->op = op;
688 inst->info = tgsi_get_opcode_info(op);
689 inst->dst[0] = dst;
690 inst->dst[1] = dst1;
691 inst->src[0] = src0;
692 inst->src[1] = src1;
693 inst->src[2] = src2;
694 inst
1641 glsl_to_tgsi_instruction *inst; local
3051 glsl_to_tgsi_instruction *inst, *new_inst; local
3263 glsl_to_tgsi_instruction *inst; local
3358 glsl_to_tgsi_instruction *inst; local
3508 glsl_to_tgsi_instruction *inst; local
3601 glsl_to_tgsi_instruction *inst; local
3951 glsl_to_tgsi_instruction *inst = NULL; local
5034 glsl_to_tgsi_instruction *inst = writes[4 * r + c]; local
5592 compile_tgsi_instruction(struct st_translate *t, const glsl_to_tgsi_instruction *inst) argument
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