/external/llvm/test/MC/Hexagon/ |
H A D | align.s | 13 r2 = sub(#1, r2) } define 15 # CHECK-NEXT: 76424022 r2 = sub(#1, r2) 21 r2 = sub(#1, r2) define 28 r2 = sub(#1, r2) define 41 #CHECK: r2 = sub(#1, r2) 46 r2 = sub(#1, r2) define [all...] |
/external/vixl/test/aarch32/ |
H A D | test-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc | 102 {{ls, r1, r2, r3}, true, ls, "ls r1 r2 r3", "ls_r1_r2_r3"}, 109 {{mi, r2, r6, r1}, true, mi, "mi r2 r6 r1", "mi_r2_r6_r1"}, 111 {{hi, r6, r0, r2}, true, hi, "hi r6 r0 r2", "hi_r6_r0_r2"}, 121 {{lt, r3, r5, r2}, true, lt, "lt r3 r5 r2", "lt_r3_r5_r2"}, 126 {{cs, r7, r2, r5}, true, cs, "cs r7 r2 r [all...] |
H A D | test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc | 98 {{cs, r0, r2, 5}, true, cs, "cs r0 r2 5", "cs_r0_r2_5"}, 101 {{cs, r5, r2, 0}, true, cs, "cs r5 r2 0", "cs_r5_r2_0"}, 103 {{ls, r2, r0, 5}, true, ls, "ls r2 r0 5", "ls_r2_r0_5"}, 109 {{vc, r5, r2, 5}, true, vc, "vc r5 r2 5", "vc_r5_r2_5"}, 111 {{cs, r2, r5, 4}, true, cs, "cs r2 r [all...] |
H A D | test-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc | 108 {{gt, r2, r2, r0}, true, gt, "gt r2 r2 r0", "gt_r2_r2_r0"}, 109 {{eq, r5, r5, r2}, true, eq, "eq r5 r5 r2", "eq_r5_r5_r2"}, 125 {{le, r2, r2, r7}, true, le, "le r2 r2 r [all...] |
H A D | test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc | 164 {{eq, r2, r2, 248}, true, eq, "eq r2 r2 248", "eq_r2_r2_248"}, 165 {{le, r2, r2, 252}, true, le, "le r2 r2 252", "le_r2_r2_252"}, 166 {{cc, r2, r2, 9 [all...] |
/external/llvm/test/MC/ARM/ |
H A D | thumb-diagnostics.s | 13 add r1, r2, r3 15 @ CHECK-ERRORS: add r1, r2, r3 19 add r2, r3 20 mov r2, r3 22 @ CHECK-ERRORS: add r2, r3 25 @ CHECK-ERRORS-V5: mov r2, r3 30 asrs r2, r3, #33 32 @ CHECK-ERRORS: asrs r2, r3, #33 59 ldm r2!, {r5, r8} 60 ldm r2, {r [all...] |
H A D | arm_addrmode3.s | 3 @ CHECK: ldrsbt r1, [r0], r2 @ encoding: [0xd2,0x10,0xb0,0xe0] 5 @ CHECK: ldrsht r1, [r0], r2 @ encoding: [0xf2,0x10,0xb0,0xe0] 7 @ CHECK: ldrht r1, [r0], r2 @ encoding: [0xb2,0x10,0xb0,0xe0] 9 @ CHECK: strht r1, [r0], r2 @ encoding: [0xb2,0x10,0xa0,0xe0] 11 ldrsbt r1, [r0], r2 13 ldrsht r1, [r0], r2 15 ldrht r1, [r0], r2 17 strht r1, [r0], r2
|
H A D | arm-it-block.s | 8 moveq r2, r3 11 @ CHECK: moveq r2, r3 @ encoding: [0x03,0x20,0xa0,0x01]
|
H A D | gas-compl-copr-reg.s | 4 @ CHECK: stc p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x02,0xed] 7 stc p14, cr6, [r2, #-224] 11 @ CHECK: stc p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x02,0xed] 14 stc p14, cr6, [r2, #-224]
|
/external/valgrind/none/tests/arm/ |
H A D | v6media.stdout.exp | 2 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 3 mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 4 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 5 mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 6 mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 7 mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 9 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 10 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 11 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 12 mla r0, r1, r2, r [all...] |
/external/capstone/suite/MC/ARM/ |
H A D | arm_addrmode3.s.cs | 2 0xd2,0x10,0xb0,0xe0 = ldrsbt r1, [r0], r2 4 0xf2,0x10,0xb0,0xe0 = ldrsht r1, [r0], r2 6 0xb2,0x10,0xb0,0xe0 = ldrht r1, [r0], r2 8 0xb2,0x10,0xa0,0xe0 = strht r1, [r0], r2
|
H A D | idiv-thumb.s.cs | 2 0x92,0xfb,0xf3,0xf1 = sdiv r1, r2, r3
|
H A D | idiv.s.cs | 2 0x12,0xf3,0x11,0xe7 = sdiv r1, r2, r3
|
/external/clang/test/Misc/ |
H A D | verify.c | 11 struct s r2; // expected-error-re {{tentative definition has type '{{.*[[:space:]]*.*}}' that is never completed}} variable in typeref:struct:s
|
/external/libxaac/decoder/armv7/ |
H A D | ixheaacd_radix4_bfly.s | 41 STR r2, [sp, #8] 45 ADD r2, r1, r3, lsl #2 54 LDR r7, [r2] 55 LDR r8, [r2, r3, lsl #2] 56 LDR r9, [r2, r3, lsl #3] 68 LDR r6, [r2, #4]! 69 LDR r9, [r2, r3, lsl #2]! 70 LDR r10, [r2, r3, lsl #2]! 93 STR r8, [r2], #-4 99 STR r8, [r2], [all...] |
H A D | ixheaacd_lap1.s | 38 SUBS r2, r2, #2 68 LDR r6, [r2], #4 69 LDR r7, [r2], #4 89 RSB r2, r2, #16 90 AND r2, r2, #0xFF 91 SUB r7, r2, #1 104 MOV r4, r4, ASR r2 [all...] |
/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
H A D | arm_addrmode3.s | 3 @ CHECK: ldrsbt r1, [r0], r2 @ encoding: [0xd2,0x10,0xb0,0xe0] 5 @ CHECK: ldrsht r1, [r0], r2 @ encoding: [0xf2,0x10,0xb0,0xe0] 7 @ CHECK: ldrht r1, [r0], r2 @ encoding: [0xb2,0x10,0xb0,0xe0] 9 @ CHECK: strht r1, [r0], r2 @ encoding: [0xb2,0x10,0xa0,0xe0] 11 ldrsbt r1, [r0], r2 13 ldrsht r1, [r0], r2 15 ldrht r1, [r0], r2 17 strht r1, [r0], r2
|
/external/swiftshader/third_party/LLVM/test/MC/MBlaze/ |
H A D | mblaze_shift.s | 12 bsrl r1, r2, r3 17 bsra r1, r2, r3 22 bsll r1, r2, r3 27 bsrli r1, r2, 0 32 bsrai r1, r2, 0 37 bslli r1, r2, 0 42 sra r1, r2 47 srl r1, r2
|
H A D | mblaze_typea.s | 12 add r1, r2, r3 17 addc r1, r2, r3 22 addk r1, r2, r3 27 addkc r1, r2, r3 32 and r1, r2, r3 37 andn r1, r2, r3 42 cmp r1, r2, r3 47 cmpu r1, r2, r3 52 idiv r1, r2, r3 57 idivu r1, r2, r [all...] |
/external/valgrind/none/tests/s390x/ |
H A D | bfp-3.c | 10 __asm__ volatile("maebr %[r1],%[r3],%[r2]" 11 : [r1]"+f"(r1) : [r2]"f"(v2), [r3]"f"(v3)); 19 __asm__ volatile("madbr %[r1],%[r3],%[r2]" 20 : [r1]"+f"(r1) : [r2]"f"(v2), [r3]"f"(v3)); 28 __asm__ volatile("msebr %[r1],%[r3],%[r2]" 29 : [r1]"+f"(r1) : [r2]"f"(v2), [r3]"f"(v3)); 37 __asm__ volatile("msdbr %[r1],%[r3],%[r2]" 38 : [r1]"+f"(r1) : [r2]"f"(v2), [r3]"f"(v3));
|
/external/valgrind/none/tests/x86/ |
H A D | incdec_alt.c | 7 int r1,r2,r3,r4,r5,r6,r7,r8,a1,a2; variable 23 "\tpopl " VG_SYM(r2) "\n" 58 r1=r2=r3=r4=r5=r6=r7=r8=0; 61 printf("0x%08x\n",r2);
|
/external/v8/src/regexp/s390/ |
H A D | regexp-macro-assembler-s390.cc | 121 __ LoadImmP(r2, Operand(FAILURE)); 156 __ LoadP(r2, register_location(reg), r0); 158 __ AddRR(r2, r0); 159 __ StoreP(r2, register_location(reg)); 167 Pop(r2); 168 __ AddP(r2, code_pointer()); 169 __ b(r2); 186 __ AddP(r2, current_input_offset(), Operand(-char_size())); 187 __ CmpP(r2, r3); 194 __ AddP(r2, current_input_offse 921 __ LoadRR(backtrack_stackpointer(), r2); local 1023 __ AddP(backtrack_stackpointer(), r2); local [all...] |
/external/clang/test/FixIt/ |
H A D | typo.c | 38 rectangle *r2 = &r1; // expected-error{{unknown type name 'rectangle'; did you mean 'Rectangle'?}} local 41 r2->top_left.y = 0;
|
/external/libcxx/test/std/utilities/function.objects/refwrap/refwrap.access/ |
H A D | conversion.pass.cpp | 28 T& r2 = r; local 29 assert(&r2 == &t);
|
/external/libcxx/test/std/utilities/function.objects/refwrap/refwrap.const/ |
H A D | copy_ctor.pass.cpp | 28 std::reference_wrapper<T> r2 = r; local 29 assert(&r2.get() == &t);
|