/external/libunwind/src/arm/ |
H A D | Gresume.c | 119 int reg; local 123 for (reg = 0; reg <= UNW_REG_LAST; ++reg) 125 Debug (16, "copying %s %d\n", unw_regname (reg), reg); 126 if (unw_is_fpreg (reg)) 128 if (tdep_access_fpreg (c, reg, &fpval, 0) >= 0) 129 as->acc.access_fpreg (as, reg, &fpval, 1, arg); 133 if (tdep_access_reg (c, reg, [all...] |
/external/libunwind/src/hppa/ |
H A D | Gresume.c | 100 int reg; local 107 for (reg = 0; reg <= UNW_REG_LAST; ++reg) 109 Debug (16, "copying %s %d\n", unw_regname (reg), reg); 110 if (unw_is_fpreg (reg)) 112 if (tdep_access_fpreg (c, reg, &fpval, 0) >= 0) 113 (*access_fpreg) (as, reg, &fpval, 1, arg); 117 if (tdep_access_reg (c, reg, [all...] |
/external/llvm/lib/CodeGen/ |
H A D | RegAllocBase.cpp | 86 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned"); 89 if (MRI->reg_nodbg_empty(VirtReg->reg)) { 92 LIS->removeInterval(VirtReg->reg); 103 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) 114 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end(); 127 VRM->assignVirt2Phys(VirtReg->reg, 128 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); 138 assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned"); 139 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) { 142 LIS->removeInterval(SplitVirtReg->reg); [all...] |
/external/capstone/arch/ARM/ |
H A D | ARMInstPrinter.h | 35 void ARM_addReg(MCInst *MI, int reg); 41 void ARM_addSysReg(MCInst *MI, arm_sysreg reg);
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/external/elfutils/libdw/ |
H A D | dwarf_frame_register.c | 56 const struct dwarf_frame_register *reg = &fs->regs[regno]; local 58 switch (reg->rule) 79 if (reg->value != 0) 81 .number = reg->value }; 82 if (reg->rule == reg_val_offset) 90 .number = reg->value }; 100 const uint8_t *p = fs->cache->data->d.d_buf + reg->value; 111 true, reg->rule == reg_val_expression,
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/external/mesa3d/src/compiler/nir/ |
H A D | nir_lower_locals_to_regs.c | 115 nir_register *reg = nir_local_reg_create(state->impl); local 116 reg->num_components = glsl_get_vector_elements(tail->type); 117 reg->num_array_elems = array_size > 1 ? array_size : 0; 118 reg->bit_size = glsl_get_bit_size(tail->type); 120 _mesa_hash_table_insert_pre_hashed(state->regs_table, hash, deref, reg); 122 return reg; 132 src.reg.reg = get_reg_for_deref(deref, state); 133 src.reg.base_offset = 0; 134 src.reg [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_wm_iz.cpp | 128 GLuint reg = 2; local 149 payload.source_depth_reg = reg; 150 reg += 2; 157 payload.aa_dest_stencil_reg = reg; 160 reg++; 164 payload.dest_depth_reg = reg; 165 reg+=2; 168 payload.num_regs = reg;
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/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | radeon_cmdbuf.h | 19 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) 20 #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2)) 88 #define OUT_BATCH_REGVAL(reg, val) \ 89 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \ 94 #define OUT_BATCH_REGSEQ(reg, count) \ 95 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
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H A D | r200_fragshader.c | 328 GLuint reg; local 333 for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) { 334 if (shader->swizzlerq & (1 << (2 * reg))) 336 set_re_cntl_d3d( ctx, reg, 1); 338 else set_re_cntl_d3d( ctx, reg, 0); 364 for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg [all...] |
H A D | r200_sanity.c | 600 struct reg { struct 612 static struct reg regs[ARRAY_SIZE(reg_names)+1]; 613 static struct reg scalars[512+1]; 614 static struct reg vectors[512*4+1]; 648 static int find_or_add_value( struct reg *reg, int val ) argument 652 for ( j = 0 ; j < reg->nvalues ; j++) 653 if ( val == reg->values[j].i ) 656 if (j == reg->nalloc) { 657 reg 707 print_int_reg_assignment( struct reg *reg, int data ) argument 731 print_float_reg_assignment( struct reg *reg, float data ) argument 762 print_reg_assignment( struct reg *reg, int data ) argument 825 struct reg *reg = lookup_reg( regs, packet[id].start + i*4 ); local 853 struct reg *reg = lookup_reg( scalars, start ); local 885 struct reg *reg = lookup_reg( scalars, start ); local 921 struct reg *reg = lookup_reg( vectors, start*4+j ); local [all...] |
/external/mesa3d/src/mesa/drivers/dri/radeon/ |
H A D | radeon_cmdbuf.h | 19 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) 20 #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2)) 88 #define OUT_BATCH_REGVAL(reg, val) \ 89 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \ 94 #define OUT_BATCH_REGSEQ(reg, count) \ 95 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
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H A D | radeon_sanity.c | 322 struct reg { struct 334 static struct reg regs[ARRAY_SIZE(reg_names)+1]; 335 static struct reg scalars[512+1]; 336 static struct reg vectors[512*4+1]; 370 static int find_or_add_value( struct reg *reg, int val ) argument 374 for ( j = 0 ; j < reg->nvalues ; j++) 375 if ( val == reg->values[j].i ) 378 if (j == reg->nalloc) { 379 reg 429 print_int_reg_assignment( struct reg *reg, int data ) argument 453 print_float_reg_assignment( struct reg *reg, float data ) argument 484 print_reg_assignment( struct reg *reg, int data ) argument 547 struct reg *reg = lookup_reg( regs, packet[id].start + i*4 ); local 575 struct reg *reg = lookup_reg( scalars, start ); local 607 struct reg *reg = lookup_reg( scalars, start ); local 643 struct reg *reg = lookup_reg( vectors, start*4+j ); local [all...] |
/external/mesa3d/src/util/ |
H A D | register_allocate.h | 54 unsigned int base_reg, unsigned int reg); 55 void ra_make_reg_conflicts_transitive(struct ra_regs *regs, unsigned int reg); 56 void ra_class_add_reg(struct ra_regs *regs, unsigned int c, unsigned int reg); 83 void ra_set_node_reg(struct ra_graph * g, unsigned int n, unsigned int reg);
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/external/mesa3d/src/gallium/drivers/vc4/ |
H A D | vc4_opt_constant_folding.c | 65 struct qreg reg = inst->src[i]; local 66 if (reg.file == QFILE_UNIF && 67 c->uniform_contents[reg.index] == QUNIFORM_CONSTANT) { 68 ui[i] = c->uniform_data[reg.index]; 69 } else if (reg.file == QFILE_SMALL_IMM) { 70 ui[i] = reg.index;
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/external/v8/src/arm/ |
H A D | constants-arm.cc | 70 const char* VFPRegisters::Name(int reg, bool is_double) { argument 71 DCHECK((0 <= reg) && (reg < kNumVFPRegisters)); 72 return names_[reg + (is_double ? kNumVFPSingleRegisters : 0)]; 104 while (aliases_[i].reg != kNoRegister) { 106 return aliases_[i].reg;
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/external/v8/src/mips/ |
H A D | constants-mips.cc | 47 const char* Registers::Name(int reg) { argument 49 if ((0 <= reg) && (reg < kNumSimuRegisters)) { 50 result = names_[reg]; 68 while (aliases_[i].reg != kInvalidRegister) { 70 return aliases_[i].reg;
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/external/v8/src/mips64/ |
H A D | constants-mips64.cc | 47 const char* Registers::Name(int reg) { argument 49 if ((0 <= reg) && (reg < kNumSimuRegisters)) { 50 result = names_[reg]; 68 while (aliases_[i].reg != kInvalidRegister) { 70 return aliases_[i].reg;
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/external/mesa3d/src/gallium/drivers/ilo/shader/ |
H A D | toy_legalize_ra.c | 46 int reg; member in struct:linear_scan_live_interval 71 linear_scan_free_regs(struct linear_scan *ls, int reg, int count) argument 76 ls->free_regs[ls->num_free_regs++] = reg + count - 1 - i; 96 int reg; local 129 reg = ls->free_regs[start]; 148 reg = -1; 153 return reg; 202 /* recycle the reg */ 203 linear_scan_free_regs(ls, interval->reg, 1); 244 int reg, coun local 532 int reg = val32 / TOY_REG_WIDTH; local 544 int reg, subreg; local 580 int reg = val32 / TOY_REG_WIDTH; local 594 int reg, subreg; local [all...] |
/external/libunwind/tests/ |
H A D | Gia64-test-stack.c | 59 int ret, reg, i, l; local 80 for (reg = 32; reg < 128; reg += 4) 85 ((ret = unw_get_reg (&c, UNW_IA64_GR + reg, &v0)) < 0 86 || (ret = unw_get_reg (&c, UNW_IA64_NAT + reg, &n0)) < 0 87 || (ret = unw_get_reg (&c, UNW_IA64_GR + reg + 1, &v1)) < 0 88 || (ret = unw_get_reg (&c, UNW_IA64_NAT + reg + 1, &n1)) < 0 89 || (ret = unw_get_reg (&c, UNW_IA64_GR + reg + 2, &v2)) < 0 90 || (ret = unw_get_reg (&c, UNW_IA64_NAT + reg [all...] |
/external/libunwind/src/ia64/ |
H A D | Ginit.c | 49 tdep_uc_addr (ucontext_t *uc, int reg, uint8_t *nat_bitnr) argument 51 return inlined_uc_addr (uc, reg, nat_bitnr); 126 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write, argument 137 switch (reg) 140 if ((ret = __uc_get_grs (uc, (reg - UNW_IA64_GR), 1, &value, &nat))) 144 ret = __uc_set_grs (uc, (reg - UNW_IA64_GR), 1, val, nat); 150 if ((ret = __uc_get_grs (uc, (reg - UNW_IA64_GR), 1, &value, &nat))) 153 mask = 1 << (reg - UNW_IA64_GR); 161 ret = __uc_set_grs (uc, (reg - UNW_IA64_GR), 1, &value, nat); 168 if (reg 246 access_fpreg(unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val, int write, void *arg) argument 281 access_reg(unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write, void *arg) argument 334 access_fpreg(unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val, int write, void *arg) argument [all...] |
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
H A D | ir3_cp.c | 160 struct ir3_register *reg = instr->regs[m]; local 161 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST)) 163 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED)) 249 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags) argument 253 reg = ir3_reg_clone(ctx->shader, reg); 259 reg->iim_val = abs(reg->iim_val); 264 reg->fim_val = fabs(reg 312 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, struct ir3_register *reg, unsigned n) argument 476 struct ir3_register *reg = instr->regs[1]; local 493 struct ir3_register *reg; local [all...] |
/external/mesa3d/src/gallium/drivers/svga/svgadump/ |
H A D | svga_shader_dump.c | 134 const struct sh_reg reg, 137 if (reg.relative) { 141 _debug_printf("%s[aL+%u]", name, reg.number); 143 _debug_printf("%s[a%u.x+%u]", name, indreg->number, reg.number); 146 _debug_printf("%s%u", name, reg.number); 150 static void dump_reg( struct sh_reg reg, struct sh_srcreg *indreg, const struct dump_info *di ) argument 152 assert( reg.is_reg == 1 ); 154 switch (sh_reg_type( reg )) { 156 format_reg("r", reg, NULL); 160 format_reg("v", reg, indre 133 format_reg(const char *name, const struct sh_reg reg, const struct sh_srcreg *indreg) argument 364 struct sh_reg reg; member in union:__anon16783 [all...] |
/external/google-breakpad/src/third_party/libdisasm/ |
H A D | ia32_reg.c | 199 void ia32_handle_register( x86_reg_t *reg, size_t id ) { argument 205 memset( reg, 0, sizeof(x86_reg_t) ); 207 strncpy( reg->name, ia32_reg_table[id].mnemonic, MAX_REGNAME ); 209 reg->type = ia32_reg_table[id].type; 210 reg->size = ia32_reg_table[id].size; 214 reg->alias = ia32_reg_aliases[alias].alias; 215 reg->shift = ia32_reg_aliases[alias].shift; 217 reg->id = id; 223 size_t reg; local 229 reg [all...] |
/external/mesa3d/src/mapi/glapi/gen/ |
H A D | gl_x86-64_asm.py | 35 for [reg, offset] in registers: 36 if reg[1:4] == "xmm": 60 for [reg, stack_offset] in registers: 61 save_reg( reg, stack_offset, adjust_stack ) 72 [reg, stack_offset] = temp.pop() 73 restore_reg(reg, stack_offset, adjust_stack) 80 def save_reg(reg, offset, use_move): 83 print '\tmovq\t%s, (%%rsp)' % (reg) 85 print '\tmovq\t%s, %u(%%rsp)' % (reg, offset) 87 print '\tpushq\t%s' % (reg) [all...] |
/external/libpcap/msdos/ |
H A D | pktdrvr.c | 150 LOCAL SWI_REGS reg; variable 156 static __dpmi_regs reg; variable 171 LOCAL struct DPMI_regs reg; variable in typeref:struct:DPMI_regs 185 } reg; variable in typeref:struct:__anon12302 312 _dx_real_int ((UINT)pktInfo.intr, ®); 313 okay = ((reg.flags & 1) == 0); /* OK if carry clear */ 316 __dpmi_int ((int)pktInfo.intr, ®); 317 okay = ((reg.x.flags & 1) == 0); 328 s.es = FP_SEG (®); 329 r.x.edi = FP_OFF (®); [all...] |