/external/llvm/test/MC/Mips/mips4/ |
H A D | invalid-mips64.s | 12 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 23 mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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H A D | invalid-mips64r2.s | 11 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 28 mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/clang/test/Sema/ |
H A D | bitfield-layout.c | 85 struct s0 { struct 90 CHECK_SIZE(struct, s0, 0x32100008) 91 CHECK_ALIGN(struct, s0, 4)
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/external/deqp/framework/qphelper/ |
H A D | qpXmlWriter.c | 281 deUint8 s0 = data[srcNdx]; local 288 d[0] = s_base64Table[s0 >> 2]; 289 d[1] = s_base64Table[((s0&0x3)<<4) | (s1>>4)];
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/external/libxcam/cl_kernel/ |
H A D | kernel_3d_denoise.cl | 74 grad.s0 = (grad.s0 + grad.s1 + grad.s2 + grad.s3); 105 dist.s0 = (distance.s0 + distance.s1 + distance.s2 + distance.s3); 107 gain = (grad.s0 < threshold) ? gain : 2.0f * gain; 108 weight = native_exp(-gain * dist.s0);
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/external/python/cpython2/Lib/ |
H A D | base64.py | 365 s0 = "Aladdin:open sesame" 366 s1 = encodestring(s0) 368 print s0, repr(s1), s2
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/external/tensorflow/tensorflow/compiler/xla/legacy_flags/ |
H A D | parse_flags_from_env.cc | 55 // Append the string s0[0, .., s0len-1] concatenated with s1[0, .., s1len-1] as 56 // a newly allocated nul-terminated string to the array *a. If s0==nullptr, a 58 static void AppendToEnvArgv(const char* s0, size_t s0len, const char* s1, argument 60 if (s0 == nullptr) { 64 string s = string(s0, s0len) + string(s1, s1len);
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/external/boringssl/src/crypto/fipsmodule/sha/ |
H A D | sha256.c | 220 s0 = X[(i + 1) & 0x0f]; \ 221 s0 = sigma0(s0); \ 224 T1 = X[(i) & 0x0f] += s0 + s1 + X[(i + 9) & 0x0f]; \ 230 uint32_t a, b, c, d, e, f, g, h, s0, s1, T1; local
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | r600_test_dma.c | 42 const uint64_t s0 = s[1]; local 43 s[0] = s0; 45 s[1] = s1 ^ s0 ^ (s1 >> 18) ^ (s0 >> 5); 46 return s[1] + s0;
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/external/libvpx/libvpx/vpx_dsp/arm/ |
H A D | loopfilter_neon.c | 544 const uint8_t *s, const int p, uint8x##w##_t *s0, uint8x##w##_t *s1, \ 550 *s0 = vld1##r##u8(s); \ 589 uint8_t *s, const int p, const uint8x##w##_t s0, const uint8x##w##_t s1, \ 591 vst1##r##u8(s, s0); \ 606 uint8_t *s, const int p, const uint8x##w##_t s0, const uint8x##w##_t s1, \ 609 vst1##r##u8(s, s0); \ 652 static INLINE void store_6x8(uint8_t *s, const int p, const uint8x8_t s0, argument 658 o0.val[0] = s0; 691 uint8_t *s, const int p, const uint8x##w##_t s0, const uint8x##w##_t s1, \ 695 vst1##r##u8(s, s0); \ 748 store_16x16(uint8_t *s, const int p, const uint8x16_t s0, const uint8x16_t s1, const uint8x16_t s2, const uint8x16_t s3, const uint8x16_t s4, const uint8x16_t s5, const uint8x16_t s6, const uint8x16_t s7, const uint8x16_t s8, const uint8x16_t s9, const uint8x16_t s10, const uint8x16_t s11, const uint8x16_t s12, const uint8x16_t s13, const uint8x16_t s14, const uint8x16_t s15) argument 845 uint8x8_t s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, local 923 uint8x8_t s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, local 1022 uint8x16_t s0, s1, s2, s3, s4, s5, s6, s7; local 1054 uint8x16_t s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, local [all...] |
H A D | idct16x16_add_neon.c | 24 static INLINE void idct_cospi_8_24_d_kernel(const int16x4_t s0, argument 28 t32[0] = vmull_lane_s16(s0, cospi_0_8_16_24, 3); 31 t32[1] = vmlal_lane_s16(t32[1], s0, cospi_0_8_16_24, 1); 34 static INLINE void idct_cospi_8_24_d(const int16x4_t s0, const int16x4_t s1, argument 39 idct_cospi_8_24_d_kernel(s0, s1, cospi_0_8_16_24, t32); 43 static INLINE void idct_cospi_8_24_neg_d(const int16x4_t s0, const int16x4_t s1, argument 49 idct_cospi_8_24_d_kernel(s0, s1, cospi_0_8_16_24, t32); 54 static INLINE void idct_cospi_16_16_d(const int16x4_t s0, const int16x4_t s1, argument 61 t32[0] = vmlsl_lane_s16(t32[2], s0, cospi_0_8_16_24, 2); 62 t32[1] = vmlal_lane_s16(t32[2], s0, cospi_0_8_16_2 [all...] |
/external/mesa3d/src/gallium/auxiliary/util/ |
H A D | u_blit.c | 256 float s0, float t0, float s1, float t1, 264 ctx->vertices[0][1][0] = s0; /*s*/ 285 ctx->vertices[3][1][0] = s0; 512 float s0, t0, s1, t1; local 523 s0 = (float) srcX0; 534 s0 /= w; 620 s0, t0, s1, t1, 252 setup_vertex_data_tex(struct blit_state *ctx, unsigned src_target, unsigned src_face, float x0, float y0, float x1, float y1, float s0, float t0, float s1, float t1, float z) argument
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/external/tensorflow/tensorflow/core/framework/ |
H A D | shape_inference.cc | 518 Status InferenceContext::Merge(ShapeHandle s0, ShapeHandle s1, argument 520 if (s0.SameHandle(s1)) { 521 *out = s0; 524 *out = s0; 525 merged_shapes_.emplace_back(s0, s1); 527 } else if (!RankKnown(s0)) { 529 merged_shapes_.emplace_back(s0, s1); 533 const int32 rank = Rank(s0); 543 auto d0 = Dim(s0, i); 559 " and ", Value(d1), ". Shapes are ", DebugString(s0), " an [all...] |
/external/libvpx/libvpx/vpx_dsp/mips/ |
H A D | itrans16_dspr2.c | 1061 int s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15; local 1089 s0 = x0 * cospi_1_64 + x1 * cospi_31_64; 1106 x0 = dct_const_round_shift(s0 + s8); 1114 x8 = dct_const_round_shift(s0 - s8); 1124 s0 = x0; 1141 x0 = s0 + s4; 1145 x4 = s0 - s4; 1159 s0 = x0; 1176 x0 = s0 + s2; 1178 x2 = s0 [all...] |
/external/llvm/test/MC/AArch64/ |
H A D | neon-diagnostics.s | 866 uqadd s0, s1, d2 874 // CHECK-ERROR: uqadd s0, s1, d2 988 sqshl s0, h1, s0 998 // CHECK-ERROR: sqshl s0, h1, s0 1009 urshl s0, s1, s2 1015 // CHECK-ERROR: urshl s0, s1, s2 1024 sqrshl b0, b1, s0 1026 sqrshl s0, s [all...] |
/external/python/cpython2/Python/ |
H A D | dtoa.c | 1360 the corresponding digits of s0. 1367 s0 points to the first significant digit of the input string. 1378 given by the bd->nd digits of s0) * 10**e0 1380 bc->nd gives the total number of significant digits of s0. It will 1383 bc->nd0 gives the number of significant digits of s0 before the 1397 bigcomp(U *rv, const char *s0, BCinfo *bc) argument 1468 /* Compare s0 with b/d: set dd to -1, 0, or 1 according as s0 < b/d, s0 == 1469 * b/d, or s0 > 1511 const char *s, *s0, *s1; local 2391 char *s, *s0; local [all...] |
/external/lzma/C/ |
H A D | Sha256.c | 36 #define s0(x) (rotrFixed(x, 7) ^ rotrFixed(x,18) ^ (x >> 3))
macro 40 #define blk2(i) (W[i] += s1(W[((i)-2)&15]) + W[((i)-7)&15] + s0(W[((i)-15)&15]))
175 #undef s0
macro
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/external/mesa3d/src/mesa/state_tracker/ |
H A D | st_cb_drawtex.c | 211 const GLfloat s0 = obj->CropRect[0] / wt; local 216 /*printf("crop texcoords: %g, %g .. %g, %g\n", s0, t0, s1, t1);*/ 217 SET_ATTRIB(0, tex_attr, s0, t0, 0.0f, 1.0f); /* lower left */ 220 SET_ATTRIB(3, tex_attr, s0, t1, 0.0f, 1.0f); /* upper left */
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/external/boringssl/src/crypto/fipsmodule/sha/asm/ |
H A D | sha512-armv4.pl | 575 my ($t0,$t1,$s0,$s1) = map("q$_",(12..15)); # temps 585 vext.8 $s0,@X[$i%8],@X[($i+1)%8],#8 @ X[i+1] 588 vshr.u64 $t0,$s0,#@sigma0[0] 590 vshr.u64 $t1,$s0,#@sigma0[1] 592 vshr.u64 $s1,$s0,#@sigma0[2] 593 vsli.64 $t0,$s0,#`64-@sigma0[0]` 594 vsli.64 $t1,$s0,#`64-@sigma0[1]` 595 vext.8 $s0,@X[($i+4)%8],@X[($i+5)%8],#8 @ X[i+9] 598 vadd.i64 @X[$i%8],$s0
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/external/honggfuzz/includes/libcommon/ |
H A D | util.c | 107 const uint64_t s0 = rndState[0]; local 109 const uint64_t result = s0 + s1; 110 s1 ^= s0; 111 rndState[0] = util_RotL(s0, 55) ^ s1 ^ (s1 << 14);
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/external/honggfuzz/libcommon/ |
H A D | util.c | 107 const uint64_t s0 = rndState[0]; local 109 const uint64_t result = s0 + s1; 110 s1 ^= s0; 111 rndState[0] = util_RotL(s0, 55) ^ s1 ^ (s1 << 14);
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/external/libcxx/test/std/strings/basic.string/string.modifiers/string_erase/ |
H A D | size_size.pass.cpp | 27 S s0 = s; local 46 assert(s == s0); 57 S s0 = s; local 76 assert(s == s0);
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/external/libxaac/decoder/drc_src/ |
H A D | impd_drc_filter_bank.h | 52 FLOAT32 s0; member in struct:__anon13021
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/external/llvm/test/MC/AMDGPU/ |
H A D | sop1.s | 24 s_mov_b32 s0, 0xfe5163ab 25 // SICI: s_mov_b32 s0, 0xfe5163ab ; encoding: [0xff,0x03,0x80,0xbe,0xab,0x63,0x51,0xfe] 26 // VI: s_mov_b32 s0, 0xfe5163ab ; encoding: [0xff,0x00,0x80,0xbe,0xab,0x63,0x51,0xfe]
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/external/llvm/test/MC/Mips/mips5/ |
H A D | invalid-mips64r2.s | 11 dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 32 mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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