| /external/clang/test/OpenMP/ |
| H A D | for_simd_reduction_messages.cpp | 53 S5(const S5 &s5) : a(s5.a) {} argument
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| H A D | parallel_for_reduction_messages.cpp | 53 S5(const S5 &s5) : a(s5.a) {} argument
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| H A D | parallel_for_simd_firstprivate_messages.cpp | 45 S5(const S5 &s5) : a(s5.a) {} // expected-note 4 {{implicitly declared private here}} argument
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| H A D | parallel_for_simd_reduction_messages.cpp | 53 S5(const S5 &s5) : a(s5.a) {} argument
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| H A D | sections_reduction_messages.cpp | 53 S5(const S5 &s5) : a(s5.a) {} argument
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| H A D | simd_reduction_messages.cpp | 53 S5(const S5 &s5) : a(s5.a) {} argument
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| H A D | target_parallel_for_firstprivate_messages.cpp | 45 S5(const S5 &s5) : a(s5.a) {} // expected-note 4 {{implicitly declared private here}} argument
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| H A D | target_parallel_for_reduction_messages.cpp | 53 S5(const S5 &s5) : a(s5.a) {} argument
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| H A D | target_parallel_for_simd_firstprivate_messages.cpp | 45 S5(const S5 &s5) : a(s5.a) {} // expected-note 4 {{implicitly declared private here}} argument
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| H A D | target_parallel_for_simd_reduction_messages.cpp | 53 S5(const S5 &s5) : a(s5.a) {} argument
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| H A D | target_parallel_map_messages.cpp | 42 S5(const S5 &s5):a(s5.a) { } argument
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| H A D | taskloop_firstprivate_messages.cpp | 45 S5(const S5 &s5) : a(s5.a) {} // expected-note 4 {{implicitly declared private here}} argument
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| H A D | taskloop_simd_firstprivate_messages.cpp | 45 S5(const S5 &s5) : a(s5.a) {} // expected-note 4 {{implicitly declared private here}} argument
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| H A D | taskloop_simd_lastprivate_messages.cpp | 50 S5(const S5 &s5) : a(s5.a) {} argument
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| H A D | teams_reduction_messages.cpp | 53 S5(const S5 &s5) : a(s5.a) {} argument
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| H A D | distribute_parallel_for_copyin_messages.cpp | 36 S5 &operator=(const S5 &s5) { return *this; } // expected-note 3 {{implicitly declared private here}} argument
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| /external/google-breakpad/src/common/android/ |
| H A D | breakpad_getcontext.S | 287 sw s5, (21 * MCONTEXT_REG_SIZE + MCONTEXT_GREGS_OFFSET)(a0)
365 sd s5, (21 * MCONTEXT_REG_SIZE + MCONTEXT_GREGS_OFFSET)(a0)
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| /external/libvpx/libvpx/vpx_dsp/arm/ |
| H A D | highbd_loopfilter_neon.c | 367 uint16x8_t *s4, uint16x8_t *s5, uint16x8_t *s6,
382 *s5 = vld1q_u16(s);
420 const uint16x8_t s5) {
431 vst1q_u16(s, s5);
463 const uint16x8_t s5) {
471 o1.val[2] = s5;
500 const uint16x8_t s5, const uint16x8_t s6) {
509 o1.val[1] = s5;
365 load_8x16(const uint16_t *s, const int p, uint16x8_t *s0, uint16x8_t *s1, uint16x8_t *s2, uint16x8_t *s3, uint16x8_t *s4, uint16x8_t *s5, uint16x8_t *s6, uint16x8_t *s7, uint16x8_t *s8, uint16x8_t *s9, uint16x8_t *s10, uint16x8_t *s11, uint16x8_t *s12, uint16x8_t *s13, uint16x8_t *s14, uint16x8_t *s15) argument
417 store_8x6(uint16_t *s, const int p, const uint16x8_t s0, const uint16x8_t s1, const uint16x8_t s2, const uint16x8_t s3, const uint16x8_t s4, const uint16x8_t s5) argument
460 store_6x8(uint16_t *s, const int p, const uint16x8_t s0, const uint16x8_t s1, const uint16x8_t s2, const uint16x8_t s3, const uint16x8_t s4, const uint16x8_t s5) argument
497 store_7x8(uint16_t *s, const int p, const uint16x8_t s0, const uint16x8_t s1, const uint16x8_t s2, const uint16x8_t s3, const uint16x8_t s4, const uint16x8_t s5, const uint16x8_t s6) argument
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| /external/llvm/test/MC/Mips/eva/ |
| H A D | invalid_R6.s | 17 swle $8,131($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
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| /external/llvm/test/MC/Mips/mips3/ |
| H A D | invalid-mips5.s | 11 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips32/ |
| H A D | invalid-mips32r2.s | 15 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips32r6/ |
| H A D | invalid-mips2.s | 31 teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips64r2.s | 17 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips64r6/ |
| H A D | invalid-mips2.s | 34 teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips3.s | 24 teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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