Searched refs:s5 (Results 226 - 250 of 303) sorted by relevance

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/external/clang/test/OpenMP/
H A Dtarget_parallel_for_simd_map_messages.cpp42 S5(const S5 &s5):a(s5.a) { } argument
H A Dtarget_map_messages.cpp336 S5(const S5 &s5):a(s5.a) { } argument
/external/libvpx/libvpx/vp8/common/x86/
H A Dloopfilter_block_sse2_x86_64.asm323 %define s5 [spp + 4 * stride]
457 punpcklbw xmm3, s5 ; 40 50
458 punpckhbw xmm5, s5 ; 48 58
766 movdqa s5, xmm10
/external/libvpx/libvpx/vpx_dsp/ppc/
H A Dvpx_convolve_vsx.c241 uint8x16_t s5 = vec_vsx_ld(0, src_y + 5 * src_stride); local
246 const uint8x16_t s = transpose_line_u8_8x8(s0, s1, s2, s3, s4, s5, s6, s7);
/external/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips2.s30 teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dvalid.s52 lh $11,-8556($s5)
97 sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
H A Dinvalid-mips5.s52 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
78 teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips3.s67 teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips32r2/
H A Dinvalid-dspr2.s40 dpaqx_sa.w.ph $ac1,$zero,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
104 precrqu_s.qb.ph $zero,$gp,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
118 shrav_r.qb $a0,$sp,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
123 subq_s.ph $13,$s8,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-dsp.s78 precrqu_s.qb.ph $zero,$gp,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
94 subq_s.ph $13,$s8,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips64.s45 teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/google-breakpad/src/testing/include/gmock/
H A Dgmock-spec-builders.h951 const Sequence& s5) {
952 return InSequence(s1, s2, s3, s4).InSequence(s5);
981 const ExpectationSet& s5) {
982 return After(s1, s2, s3, s4).After(s5);
/external/googletest/googlemock/include/gmock/
H A Dgmock-spec-builders.h961 const Sequence& s5) {
962 return InSequence(s1, s2, s3, s4).InSequence(s5);
991 const ExpectationSet& s5) {
992 return After(s1, s2, s3, s4).After(s5);
/external/llvm/test/MC/Mips/
H A Dmips64-register-names-n32-n64.s55 daddiu $s5, $zero, 0 # CHECK: encoding: [0x64,0x15,0x00,0x00]
/external/v8/testing/gmock/include/gmock/
H A Dgmock-spec-builders.h959 const Sequence& s5) {
960 return InSequence(s1, s2, s3, s4).InSequence(s5);
989 const ExpectationSet& s5) {
990 return After(s1, s2, s3, s4).After(s5);
/external/llvm/test/MC/AArch64/
H A Dbasic-a64-instructions.s1762 fcmp s3, s5
1764 // CHECK: fcmp s3, s5 // encoding: [0x60,0x20,0x25,0x1e]
1829 fneg s4, s5
1842 // CHECK: fneg s4, s5 // encoding: [0xa4,0x40,0x21,0x1e]
1892 fadd s4, s5, s6
1901 // CHECK: fadd s4, s5, s6 // encoding: [0xa4,0x28,0x26,0x1e]
1932 fmadd s3, s5, s6, s31
1934 fmsub s3, s5, s6, s31
1936 fnmadd s3, s5, s6, s31
1938 fnmsub s3, s5, s
[all...]
/external/llvm/test/MC/Mips/mips32/
H A Dvalid.s79 lh $11,-8556($s5)
153 sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
183 teqi $s5,-17504
/external/tremolo/Tremolo/
H A DmdctARM.s831 SUB r11,r10,r11,LSL #1 @ r11= s5 = x[4] - x[5]
835 ADD r2, r11,r9 @ r2 = x[0] = s5 + s3
836 SUB r4, r2, r9, LSL #1 @ r4 = x[2] = s5 - s3
860 SUB r11,r10,r11,LSL #1 @ r11= s5 = x[4] - x[5]
864 ADD r2, r11,r9 @ r2 = x[0] = s5 + s3
865 SUB r4, r2, r9, LSL #1 @ r4 = x[2] = s5 - s3
946 SUB r11,r10,r11,LSL #1 @ r11= s5 = x[4] - x[5]
950 ADD r2, r11,r9 @ r2 = x[0] = s5 + s3
951 SUB r4, r2, r9, LSL #1 @ r4 = x[2] = s5 - s3
975 SUB r11,r10,r11,LSL #1 @ r11= s5
[all...]
/external/python/cpython3/Python/
H A Ddtoa.c2310 j, j1, k, k0, k_check, leftright, m2, m5, s2, s5, local
2416 s5 = k;
2422 s5 = 0;
2645 if (s5 > 0) {
2646 S = pow5mult(S, s5);
/external/libvpx/libvpx/vp9/encoder/x86/
H A Dvp9_dct_intrin_sse2.c125 v[1] = _mm_madd_epi16(u[1], k__sinpi_p03_p04); // s4 + s5
723 __m128i s0, s1, s2, s3, s4, s5, s6, s7; local
731 s5 = _mm_sub_epi16(in[2], in[5]);
780 u0 = _mm_unpacklo_epi16(s6, s5);
781 u1 = _mm_unpackhi_epi16(s6, s5);
871 __m128i s0, s1, s2, s3, s4, s5, s6, s7; local
892 s5 = _mm_unpackhi_epi16(in4, in5);
905 u9 = _mm_madd_epi16(s5, k__cospi_p18_p14);
907 u11 = _mm_madd_epi16(s5, k__cospi_p14_m18);
1024 s5
[all...]
/external/libvpx/libvpx/vpx_dsp/x86/
H A Dinv_txfm_sse2.c123 v[1] = _mm_madd_epi16(u[1], k__sinpi_p03_p02); // s2 + s5
257 __m128i s0, s1, s2, s3, s4, s5, s6, s7; local
281 s5 = _mm_unpackhi_epi16(in4, in5);
294 u9 = _mm_madd_epi16(s5, k__cospi_p18_p14);
296 u11 = _mm_madd_epi16(s5, k__cospi_p14_m18);
413 s5 = _mm_packs_epi32(u2, u3);
434 in[6] = s5;
/external/libxcam/cl_kernel/
H A Dkernel_gauss_lap_pyramid.cl34 #define ARGS8(a) a.s0, a.s1, a.s2, a.s3, a.s4, a.s5, a.s6, a.s7
126 data.s5 = read_imagef (input, sampler, pos_start).x;
314 zoom_in.s5 = read_imagef (input_gauss1, gauss1_sampler, gauss1_pos).x;
/external/vixl/test/aarch64/
H A Dtest-api-aarch64.cc195 VIXL_CHECK(AreConsecutive(v2, b3, h4, s5));
/external/error_prone/jFormatString/
H A DjFormatString-3.0.0.jarMETA-INF/ META-INF/MANIFEST.MF edu/ edu/umd/ edu/umd/cs/ edu/umd/cs/findbugs/ ...
/external/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips32r2.s21 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

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