Searched refs:tex (Results 26 - 50 of 528) sorted by relevance

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/external/mesa3d/src/gallium/drivers/ilo/
H A Dilo_blit.h48 struct ilo_texture *tex; local
54 tex = ilo_texture(res);
61 if (tex->image.aux.type != ILO_IMAGE_AUX_HIZ ||
62 !ilo_image_can_enable_aux(&tex->image, level))
65 if (tex->image.aux.type == ILO_IMAGE_AUX_HIZ &&
66 ilo_image_can_enable_aux(&tex->image, level)) {
79 ilo_texture_set_slice_flags(tex, level,
107 surf->u.tex.level, surf->u.tex.first_layer,
108 surf->u.tex
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H A Dilo_transfer.c92 struct ilo_texture *tex = ilo_texture(res); local
96 if (tex->image.tiling == GEN8_TILING_W || tex->separate_s8) {
99 ilo_image_can_enable_aux(&tex->image, transfer->level)) {
103 } else if (tex->image_format != tex->base.format) {
116 tiled = (tex->image.tiling != GEN6_TILING_NONE);
345 tex_get_box_origin(const struct ilo_texture *tex, argument
352 ilo_image_get_slice_pos(&tex->image, level, box->z + slice, &x, &y);
356 ilo_image_pos_to_mem(&tex
360 tex_get_box_offset(const struct ilo_texture *tex, unsigned level, const struct pipe_box *box) argument
371 tex_get_slice_stride(const struct ilo_texture *tex, unsigned level) argument
518 tex_tile_choose_offset_func(const struct ilo_texture *tex, unsigned *tiles_per_row) argument
541 tex_staging_sys_map_bo(struct ilo_texture *tex, bool for_read_back, bool linear_view) argument
562 tex_staging_sys_unmap_bo(struct ilo_texture *tex) argument
568 tex_staging_sys_zs_read(struct ilo_texture *tex, const struct ilo_transfer *xfer) argument
695 tex_staging_sys_zs_write(struct ilo_texture *tex, const struct ilo_transfer *xfer) argument
822 tex_staging_sys_convert_write(struct ilo_texture *tex, const struct ilo_transfer *xfer) argument
881 struct ilo_texture *tex = ilo_texture(xfer->base.resource); local
907 struct ilo_texture *tex = ilo_texture(xfer->base.resource); local
953 const struct ilo_texture *tex = ilo_texture(xfer->base.resource); local
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H A Dilo_blitter_rectlist.c152 struct ilo_texture *tex = ilo_texture(res); local
154 blitter->fb.width = u_minify(tex->image.width0, level);
155 blitter->fb.height = u_minify(tex->image.height0, level);
170 ilo_blitter_set_fb(blitter, surf->texture, surf->u.tex.level,
184 templ.u.tex.level = level;
185 templ.u.tex.first_layer = slice;
186 templ.u.tex.last_layer = slice;
287 const struct ilo_texture *tex)
321 switch (tex->image_format) {
324 tex
286 hiz_can_clear_zs(const struct ilo_blitter *blitter, const struct ilo_texture *tex) argument
345 struct ilo_texture *tex = ilo_texture(zs->texture); local
444 struct ilo_texture *tex = ilo_texture(res); local
483 struct ilo_texture *tex = ilo_texture(res); local
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/external/mesa3d/src/gallium/auxiliary/util/
H A Du_pstipple.h41 struct pipe_resource *tex,
50 struct pipe_resource *tex);
H A Du_sampler.c50 view->u.tex.first_level = 0;
51 view->u.tex.last_level = texture->last_level;
52 view->u.tex.first_layer = 0;
53 view->u.tex.last_layer = texture->target == PIPE_TEXTURE_3D ?
/external/mesa3d/src/gallium/drivers/r300/
H A Dr300_texture_desc.h47 struct r300_resource *tex,
50 unsigned r300_texture_get_offset(struct r300_resource *tex,
H A Dr300_transfer.c87 struct pipe_resource *tex = transfer->resource; local
94 ctx->resource_copy_region(ctx, tex, transfer->level,
111 struct r300_resource *tex = r300_resource(texture); local
114 enum pipe_format format = tex->b.b.format;
118 r300->rws->cs_is_buffer_referenced(r300->cs, tex->buf, RADEON_USAGE_READWRITE);
123 !r300->rws->buffer_wait(tex->buf, 0, RADEON_USAGE_READWRITE);
137 if (tex->tex.microtile || tex->tex
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/external/skia/tests/
H A DVkWrapTests.cpp41 sk_sp<GrTexture> tex = gpu->wrapBackendTexture(origBackendTex, kBorrow_GrWrapOwnership); local
42 REPORTER_ASSERT(reporter, tex);
49 tex = gpu->wrapBackendTexture(backendTex, kBorrow_GrWrapOwnership);
50 REPORTER_ASSERT(reporter, !tex);
51 tex = gpu->wrapBackendTexture(backendTex, kAdopt_GrWrapOwnership);
52 REPORTER_ASSERT(reporter, !tex);
60 tex = gpu->wrapBackendTexture(backendTex, kBorrow_GrWrapOwnership);
61 REPORTER_ASSERT(reporter, !tex);
62 tex = gpu->wrapBackendTexture(backendTex, kAdopt_GrWrapOwnership);
63 REPORTER_ASSERT(reporter, !tex);
123 sk_sp<GrTexture> tex = local
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/external/skqp/tests/
H A DVkWrapTests.cpp41 sk_sp<GrTexture> tex = gpu->wrapBackendTexture(origBackendTex, kBorrow_GrWrapOwnership); local
42 REPORTER_ASSERT(reporter, tex);
49 tex = gpu->wrapBackendTexture(backendTex, kBorrow_GrWrapOwnership);
50 REPORTER_ASSERT(reporter, !tex);
51 tex = gpu->wrapBackendTexture(backendTex, kAdopt_GrWrapOwnership);
52 REPORTER_ASSERT(reporter, !tex);
60 tex = gpu->wrapBackendTexture(backendTex, kBorrow_GrWrapOwnership);
61 REPORTER_ASSERT(reporter, !tex);
62 tex = gpu->wrapBackendTexture(backendTex, kAdopt_GrWrapOwnership);
63 REPORTER_ASSERT(reporter, !tex);
123 sk_sp<GrTexture> tex = local
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/external/mesa3d/src/gallium/drivers/svga/
H A Dsvga_resource_texture.c229 struct svga_texture *tex = svga_texture(pt); local
233 svga_sampler_view_reference(&tex->cached_view, NULL);
236 DBG("%s deleting %p\n", __FUNCTION__, (void *) tex);
238 SVGA_DBG(DEBUG_DMA, "unref sid %p (texture)\n", tex->handle);
239 svga_screen_surface_destroy(ss, &tex->key, &tex->handle);
241 ss->hud.total_resource_bytes -= tex->size;
243 FREE(tex->defined);
244 FREE(tex->rendered_to);
245 FREE(tex
410 struct svga_texture *tex = svga_texture(texture); local
542 struct svga_texture *tex = svga_texture(texture); local
774 struct svga_texture *tex = svga_texture(transfer->resource); local
844 struct svga_texture *tex = svga_texture(transfer->resource); local
903 struct svga_texture *tex; local
1151 struct svga_texture *tex; local
1253 struct svga_texture *tex = svga_texture(pt); local
1419 struct svga_texture *tex = svga_texture(texture); local
1459 struct svga_texture *tex = svga_texture(texture); local
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H A Dsvga_sampler_view.c63 struct svga_texture *tex = svga_texture(pt); local
95 if (tex->cached_view &&
96 tex->cached_view->min_lod == min_lod &&
97 tex->cached_view->max_lod == max_lod) {
98 svga_sampler_view_reference(&sv, tex->cached_view);
133 sv->handle = tex->handle;
148 sv->age = tex->age;
149 sv->handle = svga_texture_view_surface(svga, tex,
159 sv->handle = tex->handle;
167 svga_sampler_view_reference(&tex
182 struct svga_texture *tex = svga_texture(v->texture); local
221 struct svga_texture *tex = svga_texture(v->texture); local
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/external/mesa3d/src/gallium/drivers/i915/
H A Di915_state_static.c104 struct i915_texture *tex = i915_texture(cbuf_surface->texture); local
105 assert(tex);
107 i915->current.cbuf_bo = tex->buffer;
109 BUF_3D_PITCH(tex->stride) | /* pitch in bytes */
110 buf_3d_tiling_bits(tex->tiling);
112 layer = cbuf_surface->u.tex.first_layer;
114 x = tex->image_offset[cbuf_surface->u.tex.level][layer].nblocksx;
115 y = tex->image_offset[cbuf_surface->u.tex
125 struct i915_texture *tex = i915_texture(depth_surface->texture); local
213 struct i915_texture *tex = i915_texture(depth_surface->texture); local
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H A Di915_surface.c289 struct i915_texture *tex = i915_texture(dst->texture); local
290 struct pipe_resource *pt = &tex->b.b;
292 unsigned offset = i915_texture_offset(tex, dst->u.tex.level, dst->u.tex.first_layer);
301 (unsigned short) tex->stride,
302 tex->buffer, offset,
318 struct i915_texture *tex = i915_texture(dst->texture); local
319 struct pipe_resource *pt = &tex->b.b;
322 unsigned offset = i915_texture_offset(tex, ds
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/external/mesa3d/src/gallium/state_trackers/nine/
H A Dbasetexture9.h137 struct NineBaseTexture9 *tex )
141 if (tex) {
142 if ((tex->managed.dirty | tex->dirty_mip) && LIST_IS_EMPTY(&tex->list))
143 list_add(&tex->list, &device->update_textures);
145 tex->bind_count++;
150 nine_bind(slot, tex);
/external/mesa3d/src/gallium/tests/graw/
H A Dclear.c24 struct pipe_resource *tex; variable in typeref:struct:pipe_resource
36 screen->flush_frontbuffer(screen, tex, 0, 0, window, NULL);
80 tex = screen->resource_create(screen,
82 if (tex == NULL)
86 surf_tmpl.u.tex.level = 0;
87 surf_tmpl.u.tex.first_layer = 0;
88 surf_tmpl.u.tex.last_layer = 0;
89 surf = ctx->create_surface(ctx, tex, &surf_tmpl);
/external/mesa3d/src/intel/vulkan/
H A Danv_nir_apply_pipeline_layout.c91 nir_tex_instr *tex = nir_instr_as_tex(instr); local
92 assert(tex->texture);
93 add_var_binding(state, tex->texture->var);
94 if (tex->sampler)
95 add_var_binding(state, tex->sampler->var);
132 lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref, argument
151 nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
152 tex->num_srcs + 1);
154 for (unsigned i = 0; i < tex->num_srcs; i++) {
155 new_srcs[i].src_type = tex
176 cleanup_tex_deref(nir_tex_instr *tex, nir_deref_var *deref) argument
190 lower_tex(nir_tex_instr *tex, struct apply_pipeline_layout_state *state) argument
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/external/mesa3d/src/compiler/glsl/
H A Dlower_offset_array.cpp71 ir_texture *tex = ir->clone(mem_ctx, NULL); local
72 tex->offset = new (mem_ctx) ir_dereference_array(tex->offset,
75 base_ir->insert_before(assign(var, swizzle_w(tex), 1 << i));
/external/mesa3d/src/gallium/drivers/freedreno/
H A Dfreedreno_texture.h73 void fd_setup_border_colors(struct fd_texture_stateobj *tex, void *ptr,
/external/mesa3d/src/gallium/drivers/swr/
H A Dswr_clear.cpp49 layers = std::max(layers, fb->cbufs[i]->u.tex.last_layer -
50 fb->cbufs[i]->u.tex.first_layer + 1u);
56 layers = std::max(layers, fb->zsbuf->u.tex.last_layer -
57 fb->zsbuf->u.tex.first_layer + 1u);
62 layers = std::max(layers, fb->zsbuf->u.tex.last_layer -
63 fb->zsbuf->u.tex.first_layer + 1u);
79 (fb->zsbuf->u.tex.last_layer <= fb->zsbuf->u.tex.first_layer + i))
83 if (sf && (sf->u.tex.last_layer <= sf->u.tex
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/external/mesa3d/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_surface.c40 static int amdgpu_surface_sanity(const struct pipe_resource *tex) argument
43 if (!tex->width0 || !tex->height0 || !tex->depth0 ||
44 !tex->array_size)
47 switch (tex->nr_samples) {
58 switch (tex->target) {
60 if (tex->height0 > 1)
65 if (tex->depth0 > 1 || tex
146 compute_level(struct amdgpu_winsys *ws, const struct pipe_resource *tex, struct radeon_surf *surf, bool is_stencil, unsigned level, bool compressed, ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn, ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut, ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn, ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut, ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn, ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut) argument
300 amdgpu_surface_init(struct radeon_winsys *rws, const struct pipe_resource *tex, unsigned flags, unsigned bpe, enum radeon_surf_mode mode, struct radeon_surf *surf) argument
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/external/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_surface.c94 const struct pipe_resource *tex,
103 surf_drm->npix_x = tex->width0;
104 surf_drm->npix_y = tex->height0;
105 surf_drm->npix_z = tex->depth0;
106 surf_drm->blk_w = util_format_get_blockwidth(tex->format);
107 surf_drm->blk_h = util_format_get_blockheight(tex->format);
110 surf_drm->last_level = tex->last_level;
112 surf_drm->nsamples = tex->nr_samples ? tex->nr_samples : 1;
121 switch (tex
93 surf_winsys_to_drm(struct radeon_surface *surf_drm, const struct pipe_resource *tex, unsigned flags, unsigned bpe, enum radeon_surf_mode mode, const struct radeon_surf *surf_ws) argument
222 radeon_winsys_surface_init(struct radeon_winsys *rws, const struct pipe_resource *tex, unsigned flags, unsigned bpe, enum radeon_surf_mode mode, struct radeon_surf *surf_ws) argument
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/external/mesa3d/src/gallium/drivers/softpipe/
H A Dsp_state_sampler.c188 struct pipe_resource *tex = view->texture; local
189 struct softpipe_resource *sp_tex = softpipe_resource(tex);
190 unsigned width0 = tex->width0;
191 unsigned num_layers = tex->depth0;
198 pipe_resource_reference(&mapped_tex[i], tex);
206 first_level = view->u.tex.first_level;
207 last_level = view->u.tex.last_level;
217 if (tex->target == PIPE_TEXTURE_1D_ARRAY ||
218 tex->target == PIPE_TEXTURE_2D_ARRAY ||
219 tex
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/external/mesa3d/src/mesa/main/
H A Dvdpau.c147 struct gl_texture_object *tex; local
148 tex = _mesa_lookup_texture(ctx, textureNames[i]);
149 if (tex == NULL) {
156 _mesa_lock_texture(ctx, tex);
158 if (tex->Immutable) {
159 _mesa_unlock_texture(ctx, tex);
166 if (tex->Target == 0) {
167 tex->Target = target;
168 tex->TargetIndex = _mesa_tex_target_to_index(ctx, target);
169 } else if (tex
368 struct gl_texture_object *tex = surf->textures[j]; local
422 struct gl_texture_object *tex = surf->textures[j]; local
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/external/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Ddisasm-a2xx.c388 instr_fetch_tex_t *tex = &fetch->tex; local
389 uint32_t src_swiz = tex->src_swiz;
392 if (tex->pred_select) {
396 printf(tex->pred_condition ? "EQ" : "NE");
399 print_fetch_dst(tex->dst_reg, tex->dst_swiz);
400 printf(" = R%u.", tex->src_reg);
405 printf(" CONST(%u)", tex->const_idx);
406 if (tex
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/external/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_state_sampler.c261 struct pipe_resource *tex = view->texture; local
262 struct llvmpipe_resource *lp_tex = llvmpipe_resource(tex);
263 unsigned width0 = tex->width0;
264 unsigned num_layers = tex->depth0;
274 first_level = view->u.tex.first_level;
275 last_level = view->u.tex.last_level;
285 if (tex->target == PIPE_TEXTURE_1D_ARRAY ||
286 tex->target == PIPE_TEXTURE_2D_ARRAY ||
287 tex->target == PIPE_TEXTURE_CUBE ||
288 tex
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