Searched refs:v10 (Results 1 - 25 of 132) sorted by relevance

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/external/icu/icu4j/eclipse-build/features.template/com.ibm.icu/
H A Dbuild.properties6 # http://www.eclipse.org/legal/epl-v10.html
12 epl-v10.html,\
/external/icu/icu4j/eclipse-build/features.template/com.ibm.icu.base/
H A Dbuild.properties6 # http://www.eclipse.org/legal/epl-v10.html
12 epl-v10.html,\
/external/libavc/common/armv8/
H A Dih264_deblk_chroma_av8.s102 uaddl v10.8h, v7.8b, v1.8b //Q4,Q5 = q0 + p1
111 umlal v10.8h, v3.8b, v31.8b //Q5,Q4 = (X2(q1U) + q0U + p1U)
125 rshrn v9.8b, v10.8h, #2 //Q4 = (X2(q1U) + q0U + p1U + 2) >> 2
128 rshrn v10.8b, v14.8h, #2 //
130 mov v10.d[1], v11.d[0]
132 bit v10.16b, v4.16b , v18.16b //
134 mov v11.d[0], v10.d[1]
136 st2 {v10.8b, v11.8b}, [x4], x1 //
208 mov v10.16b, v2.16b
211 mov v4.16b, v10
[all...]
H A Dih264_inter_pred_luma_horz_qpel_vert_qpel_av8.s155 ld1 {v10.2s, v11.2s}, [x7], x2 // Vector load from src[5_0]
157 uaddl v24.8h, v0.8b, v10.8b
199 umlsl v16.8h, v10.8b, v31.8b
246 umlal v16.8h, v10.8b, v30.8b
292 umlal v0.8h, v10.8b, v30.8b
342 mov v2.16b, v10.16b
359 ld1 {v10.2s, v11.2s}, [x7], x2 // Vector load from src[9_0]
361 uaddl v24.8h, v0.8b, v10.8b
401 umlsl v16.8h, v10.8b, v31.8b
446 umlal v16.8h, v10
[all...]
H A Dih264_weighted_bi_pred_av8.s174 ld1 {v10.s}[0], [x1], x4 //load row 3 in source 2
175 ld1 {v10.s}[1], [x1], x4 //load row 4 in source 2
177 uxtl v10.8h, v10.8b //converting rows 3,4 in source 2 to 16-bit
181 mla v8.8h, v10.8h , v2.h[2] //weight 2 mult. for rows 3,4
201 ld1 {v10.8b}, [x1], x4 //load row 2 in source 2
209 uxtl v10.8h, v10.8b //converting row 2 in source 2 to 16-bit
215 mla v8.8h, v10.8h , v2.h[2] //weight 2 mult. for row 2
247 ld1 {v10
[all...]
H A Dih264_weighted_pred_av8.s175 ld1 {v10.8b}, [x0], x2 //load row 4 in source
180 uxtl v10.8h, v10.8b //converting row 4 to 16-bit
183 mul v10.8h, v10.8h , v2.h[0] //weight mult. for row 4
189 srshl v10.8h, v10.8h , v0.8h //rounds off the weighted samples from row 4
194 saddw v10.8h, v10.8h , v3.8b //adding offset for row 4
197 sqxtun v10
[all...]
H A Dih264_deblk_luma_av8.s100 ld1 {v10.8b, v11.8b}, [x0], x1 //p2 values are loaded into q5
108 mov v10.d[1], v11.d[0]
125 uabd v28.16b, v10.16b, v6.16b
157 uaddl v10.8h, v16.8b, v10.8b //Q14,Q5 = p2 + (p0+q0+1)>>1
165 sub v10.8h, v10.8h , v16.8h //
169 sqshrn v28.8b, v10.8h, #1 //Q14 = i_macro_p1
258 ld1 {v10.8b, v11.8b}, [x14] //load p1 to Q5
262 mov v10
[all...]
H A Dih264_inter_pred_filters_luma_vert_av8.s136 ld1 {v10.2s, v11.2s}, [x0], x2 // Vector load from src[5_0]
140 uaddl v14.8h, v0.8b, v10.8b // temp = src[0_0] + src[5_0]
151 uaddl v18.8h, v4.8b, v10.8b
163 uaddl v12.8h, v8.8b, v10.8b
178 uaddl v12.8h, v10.8b, v0.8b
195 uaddl v16.8h, v10.8b, v4.8b // temp2 = src[1_0] + src[4_0]
217 uaddl v14.8h, v8.8b, v10.8b
220 ld1 {v10.2s, v11.2s}, [x0], x2
234 uaddl v14.8h, v10.8b, v0.8b
246 uaddl v16.8h, v10
[all...]
H A Dih264_inter_pred_luma_horz_hpel_vert_qpel_av8.s180 uaddl v10.8h, v2.8b, v3.8b
185 mla v8.8h, v10.8h , v22.8h
187 uaddl v10.8h, v1.8b, v4.8b
189 mls v8.8h, v10.8h , v24.8h
191 uaddl v10.8h, v0.8b, v5.8b
199 mla v10.8h, v12.8h , v22.8h
203 mls v10.8h, v12.8h , v24.8h
210 st1 {v10.4s}, [x9], x6 // store temp buffer 2
248 add v30.8h, v10.8h , v12.8h
276 add v28.8h, v10
[all...]
H A Dih264_inter_pred_luma_vert_qpel_av8.s143 ld1 {v10.2s, v11.2s}, [x0], x2 // Vector load from src[5_0]
147 uaddl v14.8h, v0.8b, v10.8b // temp = src[0_0] + src[5_0]
158 uaddl v18.8h, v4.8b, v10.8b
173 uaddl v12.8h, v8.8b, v10.8b
187 uaddl v12.8h, v10.8b, v0.8b
209 uaddl v16.8h, v10.8b, v4.8b // temp2 = src[1_0] + src[4_0]
234 uaddl v14.8h, v8.8b, v10.8b
237 ld1 {v10.2s, v11.2s}, [x0], x2
256 uaddl v14.8h, v10.8b, v0.8b
268 uaddl v16.8h, v10
[all...]
/external/libxaac/decoder/armv8/
H A Dixheaacd_cos_sin_mod_loop2.s109 sMULL v10.2d, v1.2s, v3.2s //qsub 1st
110 sshr v10.2d, v10.2d, #16
113 SQSUB v14.2d, v10.2d , v4.2d
114 SQSUB v16.2d, v4.2d , v10.2d
149 sMULL v10.2d, v1.2s, v3.2s //qsub 1st
150 sshr v10.2d, v10.2d, #16
153 SQSUB v14.2d, v4.2d , v10.2d
154 SQSUB v16.2d, v10
[all...]
H A Dixheaacd_inv_dit_fft_8pt.s60 SQADD v10.2s, v2.2s, v6.2s //a20_v = vqadd_s32(y1_3,y9_11);
70 SQADD v7.2s, v10.2s, v12.2s //x1_9 = vqadd_s32(a20_v,a30_v);
73 SQSUB v8.2s, v10.2s, v12.2s //x5_13 = vqsub_s32(a20_v,a30_v);
77 SQSUB v10.2s, v1.2s, v6.2s //x2_10 = vqsub_s32(a0_v,a1_v);
98 UZP1 v6.2s, v10.2s, v11.2s //x2_3
100 SQSUB v1.2s, v10.2s, v11.2s //tempr = vqsub_s32(x2_10,x3_11)
101 SQADD v5.2s, v10.2s, v11.2s //tempi = vqadd_s32(x2_10,x3_11)
104 SMULL v10.2d, v5.2s, v0.2s
107 SSHR v10.2d, v10
[all...]
H A Dixheaacd_cos_sin_mod_loop1.s72 sMULL v10.2d, v1.2s, v3.2s //qsub 1st
73 sshr v10.2d, v10.2d, #16
76 SQSUB v2.4s, v10.4s , v4.4s
109 sMULL v10.2d, v1.2s, v3.2s //qsub 1st
110 sshr v10.2d, v10.2d, #16
112 ADD v0.4s, v10.4s , v4.4s
145 sMULL v10.2d, v1.2s, v3.2s //qsub 1st
146 sshr v10
[all...]
H A Dixheaacd_post_twiddle.s58 dup v10.4h, w4
65 dup v10.4h, w4
201 uMULL v0.4s, v26.4h, v10.4h
204 uMULL v2.4s, v24.4h, v10.4h
230 sMLAL v0.4s, v27.4h, v10.4h
236 sMLAL v2.4s, v25.4h, v10.4h
238 uMULL v4.4s, v18.4h, v10.4h
239 uMULL v6.4s, v16.4h, v10.4h
251 sMLAL v4.4s, v19.4h, v10.4h
253 sMLAL v6.4s, v17.4h, v10
[all...]
/external/llvm/test/MC/AArch64/
H A Dneon-max-min.s85 fmin v10.4h, v15.4h, v22.4h
86 fmin v10.8h, v15.8h, v22.8h
87 fmin v10.2s, v15.2s, v22.2s
91 // CHECK: fmin v10.4h, v15.4h, v22.4h // encoding: [0xea,0x35,0xd6,0x0e]
92 // CHECK: fmin v10.8h, v15.8h, v22.8h // encoding: [0xea,0x35,0xd6,0x4e]
93 // CHECK: fmin v10.2s, v15.2s, v22.2s // encoding: [0xea,0xf5,0xb6,0x0e]
115 fminnm v10.4h, v15.4h, v22.4h
116 fminnm v10.8h, v15.8h, v22.8h
117 fminnm v10.2s, v15.2s, v22.2s
121 // CHECK: fminnm v10
[all...]
H A Dneon-max-min-pairwise.s85 fminp v10.4h, v15.4h, v22.4h
87 fminp v10.2s, v15.2s, v22.2s
91 // CHECK: fminp v10.4h, v15.4h, v22.4h // encoding: [0xea,0x35,0xd6,0x2e]
93 // CHECK: fminp v10.2s, v15.2s, v22.2s // encoding: [0xea,0xf5,0xb6,0x2e]
115 fminnmp v10.4h, v15.4h, v22.4h
117 fminnmp v10.2s, v15.2s, v22.2s
121 // CHECK: fminnmp v10.4h, v15.4h, v22.4h // encoding: [0xea,0x05,0xd6,0x2e]
123 // CHECK: fminnmp v10.2s, v15.2s, v22.2s // encoding: [0xea,0xc5,0xb6,0x2e]
H A Dneon-scalar-by-elem-mul.s30 fmulx s13, s21, v10.s[3]
38 // CHECK: fmulx s13, s21, v10.s[3] // encoding: [0xad,0x9a,0xaa,0x7f]
/external/clang/test/CodeGen/
H A Dvector-alignment.c52 double __attribute__((vector_size(40))) v10; variable
53 // SSE: @v10 {{.*}}, align 16
54 // AVX: @v10 {{.*}}, align 32
55 // AVX512: @v10 {{.*}}, align 64
/external/llvm/test/Object/AMDGPU/
H A Dobjdump.s36 v_add_i32_e32 v10, vcc, s8, v10
69 // CHECK: v_add_i32_e32 v10, vcc, s8, v10 // 000000000260: 32141408
/external/libhevc/common/arm64/
H A Dihevc_sao_band_offset_chroma.s163 LD1 {v10.8b},[x14],#8 //band_table_v.val[1]
223 ADD v14.8b, v10.8b , v30.8b //band_table_v.val[1] = vadd_u8(band_table_v.val[1], band_pos_v)
235 ADD v10.8b, v14.8b , v28.8b //band_table_v.val[1] = vadd_u8(band_table_v.val[1], vdup_n_u8(pi1_sao_offset_v[2]))
266 cmhs v19.8b, v29.8b , v10.8b //vcle_u8(band_table.val[1], vdup_n_u8(16))
268 ORR v10.8b, v10.8b , v19.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
280 AND v10.8b, v10.8b , v19.8b //band_table.val[1] = vand_u8(band_table.val[1], au1_cmp)
296 mov v9.d[1],v10.d[0]
297 mov v10
[all...]
H A Dihevc_inter_pred_chroma_horz.s197 ld1 { v10.2s},[x4],x11 //vector load pu1_src
240 umull v22.8h, v10.8b, v25.8b //mul_res = vmull_u8(src[0_3], coeffabs_3)//
295 ld1 { v10.2s},[x4],x11 //vector load pu1_src
354 umull v22.8h, v10.8b, v25.8b //mul_res = vmull_u8(src[0_3], coeffabs_3)//
394 ld1 { v10.2s},[x4],x11 //vector load pu1_src
425 umull v22.8h, v10.8b, v25.8b //mul_res = vmull_u8(src[0_3], coeffabs_3)//
499 umull v10.8h, v5.8b, v25.8b //mul_res = vmull_u8(src[0_3], coeffabs_3)//
500 umlsl v10.8h, v4.8b, v24.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)//
504 umlal v10.8h, v6.8b, v26.8b //mul_res = vmlsl_u8(src[0_0], coeffabs_0)//
505 umlsl v10
[all...]
H A Dihevc_itrans_recon_32x32.s211 ld1 {v10.4h},[x0],x6
230 smull v20.4s, v10.4h, v0.h[0]
234 smull v22.4s, v10.4h, v0.h[0]
237 smull v16.4s, v10.4h, v0.h[0]
240 smull v18.4s, v10.4h, v0.h[0]
280 ld1 {v10.4h},[x0],x6
300 smlal v20.4s, v10.4h, v2.h[0]
304 smlal v22.4s, v10.4h, v6.h[0]
307 smlsl v16.4s, v10.4h, v6.h[0]
310 smlsl v18.4s, v10
[all...]
H A Dihevc_intra_pred_chroma_mode_27_to_33.s169 umull v10.8h, v23.8b, v30.8b //(i row)vmull_u8(ref_main_idx, dup_const_32_fract)
172 umlal v10.8h, v9.8b, v31.8b //(i row)vmull_u8(ref_main_idx_1, dup_const_fract)
187 rshrn v10.8b, v10.8h,#5 //(i row)shift_res = vrshrn_n_u16(add_res, 5)
201 st1 {v10.8b},[x2],#8 //(i row)
230 umull v10.8h, v23.8b, v30.8b //(v)vmull_u8(ref_main_idx, dup_const_32_fract)
233 umlal v10.8h, v9.8b, v31.8b //(v)vmull_u8(ref_main_idx_1, dup_const_fract)
253 rshrn v10.8b, v10.8h,#5 //(v)shift_res = vrshrn_n_u16(add_res, 5)
267 st1 {v10
[all...]
H A Dihevc_intra_pred_filters_luma_mode_19_to_25.s284 umull v10.8h, v23.8b, v30.8b //(i row)vmull_u8(ref_main_idx, dup_const_32_fract)
287 umlal v10.8h, v9.8b, v31.8b //(i row)vmull_u8(ref_main_idx_1, dup_const_fract)
301 rshrn v10.8b, v10.8h,#5 //(i row)shift_res = vrshrn_n_u16(add_res, 5)
315 st1 {v10.8b},[x2],#8 //(i row)
342 umull v10.8h, v23.8b, v30.8b //(v)vmull_u8(ref_main_idx, dup_const_32_fract)
345 umlal v10.8h, v9.8b, v31.8b //(v)vmull_u8(ref_main_idx_1, dup_const_fract)
364 rshrn v10.8b, v10.8h,#5 //(v)shift_res = vrshrn_n_u16(add_res, 5)
378 st1 {v10
[all...]
H A Dihevc_intra_pred_luma_mode_27_to_33.s174 umull v10.8h, v23.8b, v30.8b //(i row)vmull_u8(ref_main_idx, dup_const_32_fract)
177 umlal v10.8h, v9.8b, v31.8b //(i row)vmull_u8(ref_main_idx_1, dup_const_fract)
192 rshrn v10.8b, v10.8h,#5 //(i row)shift_res = vrshrn_n_u16(add_res, 5)
206 st1 {v10.8b},[x2],#8 //(i row)
235 umull v10.8h, v23.8b, v30.8b //(v)vmull_u8(ref_main_idx, dup_const_32_fract)
238 umlal v10.8h, v9.8b, v31.8b //(v)vmull_u8(ref_main_idx_1, dup_const_fract)
258 rshrn v10.8b, v10.8h,#5 //(v)shift_res = vrshrn_n_u16(add_res, 5)
272 st1 {v10
[all...]

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