/external/v8/src/s390/ |
H A D | simulator-s390.cc | 2385 // Test src1 and src2 have opposite sign, 2390 #define CheckOverflowForIntAdd(src1, src2, type) \ 2391 OverflowFromSigned<type>(src1 + src2, src1, src2, true); 2393 #define CheckOverflowForIntSub(src1, src2, type) \ 2394 OverflowFromSigned<type>(src1 - src2, src1, src2, false); 2397 #define CheckOverflowForUIntAdd(src1, src2) \ 2398 ((src1) + (src2) < (src1) || (src [all...] |
/external/v8/src/x64/ |
H A D | assembler-x64.cc | 3957 void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1, argument 3961 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW1); 3967 void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1, argument 3971 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW1); 3977 void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1, argument 3981 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW0); 3987 void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1, argument 3991 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW0); 4054 void Assembler::vinstr(byte op, XMMRegister dst, XMMRegister src1, argument 4059 emit_vex_prefix(dst, src1, src 4064 vinstr(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2, SIMDPrefix pp, LeadingOpcode m, VexW w) argument 4075 vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument 4085 vps(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument 4095 vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument 4105 vpd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument 4133 vss(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument 4143 vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument [all...] |
H A D | assembler-x64.h | 1070 void vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2, 1072 void vinstr(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2, 1092 void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \ 1093 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \ 1095 void v##instruction(XMMRegister dst, XMMRegister src1, \ 1097 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \ 1143 void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \ 1144 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \ 1146 void v##instruction(XMMRegister dst, XMMRegister src1, \ 1148 vinstr(0x##opcode, dst, src1, src [all...] |
H A D | macro-assembler-x64.cc | 1390 void MacroAssembler::SmiOrIfSmis(Register dst, Register src1, Register src2, 1393 if (dst.is(src1) || dst.is(src2)) { 1394 DCHECK(!src1.is(kScratchRegister)); 1396 movp(kScratchRegister, src1); 1401 movp(dst, src1); 1599 void MacroAssembler::JumpIfNotBothSmi(Register src1, 1603 Condition both_smi = CheckBothSmi(src1, src2); 1608 void MacroAssembler::JumpUnlessBothNonNegativeSmi(Register src1, 1612 Condition both_smi = CheckBothNonNegativeSmi(src1, src2); 1785 Register src1, 1783 SmiAddHelper(MacroAssembler* masm, Register dst, Register src1, T src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1805 SmiAdd(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1816 SmiAdd(Register dst, Register src1, const Operand& src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1827 SmiAdd(Register dst, Register src1, Register src2) argument 1847 SmiSubHelper(MacroAssembler* masm, Register dst, Register src1, T src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1869 SmiSub(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1880 SmiSub(Register dst, Register src1, const Operand& src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1892 SmiSubNoOverflowHelper(MacroAssembler* masm, Register dst, Register src1, T src2) argument 1906 SmiSub(Register dst, Register src1, Register src2) argument 1912 SmiSub(Register dst, Register src1, const Operand& src2) argument 1919 SmiMul(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1974 SmiDiv(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 2037 SmiMod(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 2113 SmiAnd(Register dst, Register src1, Register src2) argument 2136 SmiOr(Register dst, Register src1, Register src2) argument 2157 SmiXor(Register dst, Register src1, Register src2) argument 2246 SmiShiftLeft(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 2297 SmiShiftLogicalRight(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 2334 SmiShiftArithmeticRight(Register dst, Register src1, Register src2) argument 2352 SelectNonSmi(Register dst, Register src1, Register src2, Label* on_not_smis, Label::Distance near_jump) argument 2950 Ucomiss(XMMRegister src1, XMMRegister src2) argument 2960 Ucomiss(XMMRegister src1, const Operand& src2) argument 2970 Ucomisd(XMMRegister src1, XMMRegister src2) argument 2980 Ucomisd(XMMRegister src1, const Operand& src2) argument [all...] |
H A D | macro-assembler-x64.h | 472 Register src1, 570 void JumpIfNotBothSmi(Register src1, 576 void JumpUnlessBothNonNegativeSmi(Register src1, Register src2, 618 // If dst is src1, then src1 will be destroyed if the operation is 621 Register src1, 626 Register src1, 632 Register src1, 636 // If dst is src1, then src1 wil [all...] |
/external/tensorflow/tensorflow/core/kernels/ |
H A D | mkl_aggregate_ops.cc | 359 MklDnnData<T> src1(&cpu_engine); 414 src1.SetUsrMem(md1, &src1_tensor); 450 src1.CheckReorderToOpMem(srcs_pd[0], &net); 452 inputs.push_back(src1.GetOpMem());
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/external/swiftshader/third_party/subzero/src/ |
H A D | IceTargetLoweringARM32.cpp | 2445 Operand *src1() const { return Src1; } function in class:__anon23512::NumericOperandsBase 3442 ConstantInteger32 *ShAmt = llvm::cast<ConstantInteger32>(Srcs.src1()); 3466 ConstantInteger32 *ShAmt = llvm::cast<ConstantInteger32>(Srcs.src1()); 3491 ConstantInteger32 *ShAmt = llvm::cast<ConstantInteger32>(Srcs.src1());
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86GenDAGISel.inc | 2439 /*5380*/ OPC_RecordChild1, // #3 = $src1
2456 // Src: (st (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src1), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 50
2457 // Dst: (ROL8mi:i32 addr:iPTR:$dst, (imm:i8):$src1)
2462 /*5428*/ OPC_RecordChild1, // #3 = $src1
2479 // Src: (st (rotl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src1), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 50
2480 // Dst: (ROL16mi:i32 addr:iPTR:$dst, (imm:i8):$src1)
2484 /*5475*/ OPC_RecordChild1, // #3 = $src1
2501 // Src: (st (rotl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src1), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 50
2502 // Dst: (ROL32mi:i32 addr:iPTR:$dst, (imm:i8):$src1)
2506 /*5522*/ OPC_RecordChild1, // #3 = $src1
[all...] |
/external/swiftshader/src/Shader/ |
H A D | PixelPipeline.cpp | 88 const Src &src1 = instruction->src[1]; local 101 if(src1.type != Shader::PARAMETER_VOID) s1 = fetchRegister(src1); 1458 void PixelPipeline::ADD(Vector4s &dst, Vector4s &src0, Vector4s &src1) 1460 dst.x = AddSat(src0.x, src1.x); 1461 dst.y = AddSat(src0.y, src1.y); 1462 dst.z = AddSat(src0.z, src1.z); 1463 dst.w = AddSat(src0.w, src1.w); 1466 void PixelPipeline::SUB(Vector4s &dst, Vector4s &src0, Vector4s &src1) 1468 dst.x = SubSat(src0.x, src1 [all...] |
H A D | PixelPipeline.hpp | 75 void ADD(Vector4s &dst, Vector4s &src0, Vector4s &src1); 76 void SUB(Vector4s &dst, Vector4s &src0, Vector4s &src1); 77 void MAD(Vector4s &dst, Vector4s &src0, Vector4s &src1, Vector4s &src2); 78 void MUL(Vector4s &dst, Vector4s &src0, Vector4s &src1); 79 void DP3(Vector4s &dst, Vector4s &src0, Vector4s &src1); 80 void DP4(Vector4s &dst, Vector4s &src0, Vector4s &src1); 81 void LRP(Vector4s &dst, Vector4s &src0, Vector4s &src1, Vector4s &src2); 100 void TEXM3X3SPEC(Vector4s &dst, Float4 &u, Float4 &v, Float4 &s, int stage, Vector4s &src0, Vector4s &src1); 104 void CND(Vector4s &dst, Vector4s &src0, Vector4s &src1, Vector4s &src2); 105 void CMP(Vector4s &dst, Vector4s &src0, Vector4s &src1, Vector4 [all...] |
H A D | PixelProgram.cpp | 112 const Src &src1 = instruction->src[1]; local 146 if(src1.type != Shader::PARAMETER_VOID) s1 = fetchRegister(src1); 281 case Shader::OPCODE_M4X4: M4X4(d, s0, src1); break; 282 case Shader::OPCODE_M4X3: M4X3(d, s0, src1); break; 283 case Shader::OPCODE_M3X4: M3X4(d, s0, src1); break; 284 case Shader::OPCODE_M3X3: M3X3(d, s0, src1); break; 285 case Shader::OPCODE_M3X2: M3X2(d, s0, src1); break; 286 case Shader::OPCODE_TEX: TEX(d, s0, src1, project, bias); break; 287 case Shader::OPCODE_TEXLDD: TEXGRAD(d, s0, src1, s 1061 M3X2(Vector4f &dst, Vector4f &src0, const Src &src1) argument 1070 M3X3(Vector4f &dst, Vector4f &src0, const Src &src1) argument 1081 M3X4(Vector4f &dst, Vector4f &src0, const Src &src1) argument 1094 M4X3(Vector4f &dst, Vector4f &src0, const Src &src1) argument 1105 M4X4(Vector4f &dst, Vector4f &src0, const Src &src1) argument 1118 TEX(Vector4f &dst, Vector4f &src0, const Src &src1, bool project, bool bias) argument 1136 TEXOFFSET(Vector4f &dst, Vector4f &src0, const Src &src1, Vector4f &offset) argument 1141 TEXLODOFFSET(Vector4f &dst, Vector4f &src0, const Src &src1, Vector4f &offset, Float4 &lod) argument 1146 TEXBIAS(Vector4f &dst, Vector4f &src0, const Src &src1, Float4 &bias) argument 1151 TEXOFFSETBIAS(Vector4f &dst, Vector4f &src0, const Src &src1, Vector4f &offset, Float4 &bias) argument 1156 TEXELFETCH(Vector4f &dst, Vector4f &src0, const Src& src1, Float4 &lod) argument 1161 TEXELFETCHOFFSET(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &offset, Float4 &lod) argument 1166 TEXGRAD(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &dsx, Vector4f &dsy) argument 1171 TEXGRADOFFSET(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &dsx, Vector4f &dsy, Vector4f &offset) argument 1176 TEXLOD(Vector4f &dst, Vector4f &src0, const Src &src1, Float4 &lod) argument 1181 TEXSIZE(Vector4f &dst, Float4 &lod, const Src &src1) argument 1257 BREAKC(Vector4f &src0, Vector4f &src1, Control control) argument [all...] |
H A D | PixelProgram.hpp | 104 void M3X2(Vector4f &dst, Vector4f &src0, const Src &src1); 105 void M3X3(Vector4f &dst, Vector4f &src0, const Src &src1); 106 void M3X4(Vector4f &dst, Vector4f &src0, const Src &src1); 107 void M4X3(Vector4f &dst, Vector4f &src0, const Src &src1); 108 void M4X4(Vector4f &dst, Vector4f &src0, const Src &src1); 109 void TEX(Vector4f &dst, Vector4f &src0, const Src &src1, bool project, bool bias); 110 void TEXLOD(Vector4f &dst, Vector4f &src0, const Src &src1, Float4 &lod); 111 void TEXBIAS(Vector4f &dst, Vector4f &src0, const Src &src1, Float4 &bias); 112 void TEXSIZE(Vector4f &dst, Float4 &lod, const Src &src1); 114 void TEXOFFSET(Vector4f &dst, Vector4f &src0, const Src &src1, Vector4 [all...] |
H A D | Shader.cpp | 1855 Parameter &src1 = inst->src[1]; 1859 usedSamplers |= 1 << src1.index;
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H A D | ShaderCore.cpp | 659 void ShaderCore::add(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 661 dst.x = src0.x + src1.x; 662 dst.y = src0.y + src1.y; 663 dst.z = src0.z + src1.z; 664 dst.w = src0.w + src1.w; 667 void ShaderCore::iadd(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 669 dst.x = As<Float4>(As<Int4>(src0.x) + As<Int4>(src1.x)); 670 dst.y = As<Float4>(As<Int4>(src0.y) + As<Int4>(src1.y)); 671 dst.z = As<Float4>(As<Int4>(src0.z) + As<Int4>(src1.z)); 672 dst.w = As<Float4>(As<Int4>(src0.w) + As<Int4>(src1 675 sub(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 683 isub(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 691 mad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 699 imad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 707 mul(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 715 imul(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 733 div(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 741 idiv(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 754 udiv(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 767 mod(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 775 imod(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 788 umod(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 801 shl(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 809 ishr(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 817 ushr(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 866 dist1(Float4 &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 871 dist2(Float4 &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 879 dist3(Float4 &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 888 dist4(Float4 &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 898 dp1(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 908 dp2(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 918 dp2add(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 928 dp3(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 938 dp4(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 948 min(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 956 imin(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 964 umin(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 972 max(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 980 imax(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 988 umax(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 996 slt(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1082 att(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1091 lrp(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 1202 det2(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1208 det3(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 1214 det4(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2, const Vector4f &src3) argument 1289 powx(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 1299 pow(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 1307 crs(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1547 atan2(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 1652 cmp0(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 1660 select(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 1668 extract(Float4 &dst, const Vector4f &src0, const Float4 &src1) argument 1697 cmp0(Float4 &dst, const Float4 &src0, const Float4 &src1, const Float4 &src2) argument 1703 cmp0i(Float4 &dst, const Float4 &src0, const Float4 &src1, const Float4 &src2) argument 1709 select(Float4 &dst, RValue<Int4> src0, const Float4 &src1, const Float4 &src2) argument 1715 cmp(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, Control control) argument 1760 icmp(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, Control control) argument 1805 ucmp(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, Control control) argument 1868 bitwise_or(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1876 bitwise_xor(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1884 bitwise_and(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1892 equal(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1903 notEqual(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument [all...] |
H A D | ShaderCore.hpp | 233 void add(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 234 void iadd(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 235 void sub(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 236 void isub(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 237 void mad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2); 238 void imad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2); 239 void mul(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 240 void imul(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 242 void div(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 243 void idiv(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); [all...] |
H A D | VertexPipeline.cpp | 937 Float4 VertexPipeline::power(Float4 &src0, Float4 &src1) argument 945 dst *= src1;
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H A D | VertexPipeline.hpp | 41 Float4 power(Float4 &src0, Float4 &src1);
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H A D | VertexProgram.cpp | 130 Src src1 = instruction->src[1]; local 148 if(src1.type != Shader::PARAMETER_VOID) s1 = fetchRegister(src1); 222 case Shader::OPCODE_M3X2: M3X2(d, s0, src1); break; 223 case Shader::OPCODE_M3X3: M3X3(d, s0, src1); break; 224 case Shader::OPCODE_M3X4: M3X4(d, s0, src1); break; 225 case Shader::OPCODE_M4X3: M4X3(d, s0, src1); break; 226 case Shader::OPCODE_M4X4: M4X4(d, s0, src1); break; 310 case Shader::OPCODE_LOOP: LOOP(src1); break; 330 case Shader::OPCODE_TEXLDL: TEXLOD(d, s0, src1, s 954 M3X2(Vector4f &dst, Vector4f &src0, Src &src1) argument 963 M3X3(Vector4f &dst, Vector4f &src0, Src &src1) argument 974 M3X4(Vector4f &dst, Vector4f &src0, Src &src1) argument 987 M4X3(Vector4f &dst, Vector4f &src0, Src &src1) argument 998 M4X4(Vector4f &dst, Vector4f &src0, Src &src1) argument 1016 BREAKC(Vector4f &src0, Vector4f &src1, Control control) argument 1515 TEX(Vector4f &dst, Vector4f &src0, const Src &src1) argument 1520 TEXOFFSET(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &offset) argument 1525 TEXLOD(Vector4f &dst, Vector4f &src0, const Src& src1, Float4 &lod) argument 1530 TEXLODOFFSET(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &offset, Float4 &lod) argument 1535 TEXELFETCH(Vector4f &dst, Vector4f &src0, const Src& src1, Float4 &lod) argument 1540 TEXELFETCHOFFSET(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &offset, Float4 &lod) argument 1545 TEXGRAD(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &dsx, Vector4f &dsy) argument 1550 TEXGRADOFFSET(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &dsx, Vector4f &dsy, Vector4f &offset) argument 1555 TEXSIZE(Vector4f &dst, Float4 &lod, const Src &src1) argument [all...] |
H A D | VertexProgram.hpp | 77 void M3X2(Vector4f &dst, Vector4f &src0, Src &src1); 78 void M3X3(Vector4f &dst, Vector4f &src0, Src &src1); 79 void M3X4(Vector4f &dst, Vector4f &src0, Src &src1); 80 void M4X3(Vector4f &dst, Vector4f &src0, Src &src1); 81 void M4X4(Vector4f &dst, Vector4f &src0, Src &src1); 83 void BREAKC(Vector4f &src0, Vector4f &src1, Control); 101 void IFC(Vector4f &src0, Vector4f &src1, Control);
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/external/swiftshader/src/OpenGL/compiler/ |
H A D | OutputASM.cpp | 2049 Instruction *OutputASM::emit(sw::Shader::Opcode op, TIntermTyped *dst, TIntermNode *src0, TIntermNode *src1, TIntermNode *src2, TIntermNode *src3, TIntermNode *src4) argument 2051 return emit(op, dst, 0, src0, 0, src1, 0, src2, 0, src3, 0, src4, 0); 2054 Instruction *OutputASM::emit(sw::Shader::Opcode op, TIntermTyped *dst, int dstIndex, TIntermNode *src0, int index0, TIntermNode *src1, int index1, argument 2071 source(instruction->src[1], src1, index1); 2135 void OutputASM::emitBinary(sw::Shader::Opcode op, TIntermTyped *dst, TIntermNode *src0, TIntermNode *src1, TIntermNode *src2) argument 2139 emit(op, dst, index, src0, index, src1, index, src2, index); 2143 void OutputASM::emitAssign(sw::Shader::Opcode op, TIntermTyped *result, TIntermTyped *lhs, TIntermTyped *src0, TIntermTyped *src1) argument 2145 emitBinary(op, result, src0, src1);
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H A D | OutputASM.h | 269 Instruction *emit(sw::Shader::Opcode op, TIntermTyped *dst = 0, TIntermNode *src0 = 0, TIntermNode *src1 = 0, TIntermNode *src2 = 0, TIntermNode *src3 = 0, TIntermNode *src4 = 0); 270 Instruction *emit(sw::Shader::Opcode op, TIntermTyped *dst, int dstIndex, TIntermNode *src0 = 0, int index0 = 0, TIntermNode *src1 = 0, int index1 = 0, 274 void emitBinary(sw::Shader::Opcode op, TIntermTyped *dst = 0, TIntermNode *src0 = 0, TIntermNode *src1 = 0, TIntermNode *src2 = 0); 275 void emitAssign(sw::Shader::Opcode op, TIntermTyped *result, TIntermTyped *lhs, TIntermTyped *src0, TIntermTyped *src1 = 0);
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/external/skqp/tests/ |
H A D | CPlusPlusEleven.cpp | 29 Moveable src1; Moveable dst1(std::move(src1)); local
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/external/skqp/src/core/ |
H A D | SkBitmapProcState.cpp | 630 SkPMColor src1 = src[SkFractionalIntToInt(fx)]; fx += dx; 634 dst[1] = src1;
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H A D | SkGeometry.cpp | 720 const SkScalar src1[] = { 0, 0 }; 732 { TEST_COLLAPS_ENTRY(src1), 1 },
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/external/skqp/samplecode/ |
H A D | SamplePolyToPoly.cpp | 41 const SkScalar src1[] = { local 49 (void) m2.setPolyToPoly((const SkPoint*)src1, (SkPoint*)dst1, 4); 125 const int src1[] = { 0, 0 }; local 127 doDraw(canvas, &paint, src1, dst1, 1);
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