| /art/compiler/optimizing/ |
| H A D | common_arm.h | 42 return dwarf::Reg::ArmCore(static_cast<int>(reg.GetCode()));
46 return dwarf::Reg::ArmFp(static_cast<int>(reg.GetCode()));
159 vixl::aarch32::DRegister d = vixl::aarch32::DRegister(s.GetCode() / 2);
213 return Location::RegisterLocation(reg.GetCode());
217 return Location::FpuRegisterLocation(reg.GetCode());
222 return Location::RegisterPairLocation(low.GetCode(), high.GetCode());
227 return Location::FpuRegisterPairLocation(low.GetCode(), high.GetCode());
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| H A D | optimizing_compiler.cc | 1147 jni_compiled_method.GetCode(),
1220 jni_compiled_method.GetCode().data(),
1221 jni_compiled_method.GetCode().size(),
1234 const uintptr_t code_address = reinterpret_cast<uintptr_t>(method_header->GetCode());
1248 info.code_size = jni_compiled_method.GetCode().size();
1257 jit_logger->WriteLog(code, jni_compiled_method.GetCode().size(), method);
1358 const uintptr_t code_address = reinterpret_cast<uintptr_t>(method_header->GetCode());
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| H A D | code_generator_arm64.h | 96 ? vixl::aarch64::x21.GetCode()
97 : vixl::aarch64::x20.GetCode()),
98 vixl::aarch64::x30.GetCode());
101 vixl::aarch64::d8.GetCode(),
102 vixl::aarch64::d15.GetCode());
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| H A D | common_arm64.h | 209 return Location::RegisterLocation(ARTRegCodeFromVIXL(reg.GetCode()));
213 return Location::FpuRegisterLocation(fpreg.GetCode());
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| H A D | code_generator_arm_vixl.cc | 119 DCHECK_EQ(kBakerCcEntrypointRegister.GetCode(),
155 DCHECK_EQ(raw_adr[3] & 0x8fu, rd_.GetCode()); // Check bits 8-11 and 15.
785 Thread::ReadBarrierMarkEntryPointsOffset<kArmPointerSize>(ref_reg.GetCode());
894 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(ref_reg.GetCode())) << ref_reg;
1046 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(ref_reg.GetCode())) << ref_reg;
1250 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(reg_out.GetCode()));
1277 DCHECK(locations->GetLiveRegisters()->ContainsCoreRegister(index_reg.GetCode()));
1278 if (codegen->IsCoreCalleeSaveRegister(index_reg.GetCode())) {
1375 uint32_t ref = RegisterFrom(ref_).GetCode();
1376 uint32_t obj = RegisterFrom(obj_).GetCode();
[all...] |
| H A D | code_generator_arm64.cc | 109 return Location::RegisterLocation(x15.GetCode());
1264 size_t ref = static_cast<int>(XRegisterFrom(ref_).GetCode());
1265 size_t obj = static_cast<int>(XRegisterFrom(obj_).GetCode());
1624 blocked_core_registers_[reserved_core_registers.PopLowestIndex().GetCode()] = true;
1629 blocked_fpu_registers_[reserved_fp_registers.PopLowestIndex().GetCode()] = true;
1638 blocked_fpu_registers_[reserved_fp_registers_debuggable.PopLowestIndex().GetCode()] = true;
3074 caller_saves.Add(Location::RegisterLocation(calling_convention.GetRegisterAt(0).GetCode()));
3075 caller_saves.Add(Location::RegisterLocation(calling_convention.GetRegisterAt(1).GetCode()));
3692 caller_saves.Add(Location::RegisterLocation(calling_convention.GetRegisterAt(0).GetCode()));
4827 caller_saves.Add(Location::RegisterLocation(calling_convention.GetRegisterAt(0).GetCode()));
[all...] |
| H A D | intrinsics_arm64.cc | 2960 Location::RegisterLocation(calling_convention.GetRegisterAt(0).GetCode()));
|
| H A D | intrinsics_arm_vixl.cc | 230 Thread::ReadBarrierMarkEntryPointsOffset<kArmPointerSize>(tmp.GetCode());
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| /art/disassembler/ |
| H A D | disassembler_arm64.cc | 48 if (reg.GetCode() == TR) {
51 } else if (reg.GetCode() == LR) {
|
| /art/compiler/utils/arm/ |
| H A D | assembler_arm_vixl.cc | 255 CHECK_NE(base.GetCode(), kIpCode);
256 if ((reg.GetCode() != kIpCode) &&
258 ((type != kStoreWordPair) || (reg.GetCode() + 1 != kIpCode))) {
267 tmp_reg = (base.GetCode() != 5) ? r5 : r6;
269 if (base.GetCode() == kSpCode) {
290 ___ Strd(reg, vixl32::Register(reg.GetCode() + 1), MemOperand(base, offset));
296 if ((tmp_reg.IsValid()) && (tmp_reg.GetCode() != kIpCode)) {
351 ___ Ldrd(dest, vixl32::Register(dest.GetCode() + 1), MemOperand(base, offset));
395 DCHECK_EQ(regs & (1u << base.GetCode()), 0u);
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| H A D | jni_macro_assembler_arm_vixl.cc | 49 return dwarf::Reg::ArmCore(static_cast<int>(reg.GetCode()));
53 return dwarf::Reg::ArmFp(static_cast<int>(reg.GetCode()));
177 DCHECK_EQ(core_spill_mask & (1 << temp.GetCode()), 0)
178 << "core_spill_mask hould not contain scratch register R" << temp.GetCode();
|
| /art/compiler/jni/quick/ |
| H A D | jni_compiler.h | 50 ArrayRef<const uint8_t> GetCode() const { return ArrayRef<const uint8_t>(code_); } function in class:art::JniCompiledMethod
|
| /art/compiler/utils/arm64/ |
| H A D | assembler_arm64.cc | 76 return dwarf::Reg::Arm64Fp(reg.GetCode());
78 DCHECK_LT(reg.GetCode(), 31u); // X0 - X30.
79 return dwarf::Reg::Arm64Core(reg.GetCode());
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| H A D | jni_macro_assembler_arm64.cc | 696 core_reg_list.Combine(reg_x(reg.AsXRegister()).GetCode());
699 fp_reg_list.Combine(reg_d(reg.AsDRegister()).GetCode());
753 core_reg_list.Combine(reg_x(reg.AsXRegister()).GetCode());
756 fp_reg_list.Combine(reg_d(reg.AsDRegister()).GetCode());
789 << "core_reg_list should contain Marking Register X" << mr.GetCode();
801 << "core_reg_list should not contain scratch register X" << temp.GetCode();
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| /art/compiler/linker/arm/ |
| H A D | relative_patcher_thumb2.cc | 215 DCHECK_EQ(entrypoint.GetCode(), Thumb2RelativePatcher::kBakerCcEntrypointRegister);
217 DCHECK_EQ(ip.GetCode(), 12u);
219 Thread::ReadBarrierMarkEntryPointsOffset<kArmPointerSize>(ip.GetCode());
234 CheckValidReg(base_reg.GetCode());
236 CheckValidReg(holder_reg.GetCode());
285 CheckValidReg(base_reg.GetCode());
317 CheckValidReg(root_reg.GetCode());
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| H A D | relative_patcher_arm_base.cc | 47 ArrayRef<const uint8_t> GetCode() const { function in class:art::linker::ArmBaseRelativePatcher::ThunkData
210 if (UNLIKELY(!WriteThunk(out, pending_thunks_.front()->GetCode()))) {
|
| /art/runtime/jit/ |
| H A D | jit_code_cache.cc | 115 const void* GetCode() const { function in class:art::jit::JitCodeCache::JniStubData
120 return GetCode() != nullptr;
343 return data.GetCode();
600 FreeCode(method_header->GetCode());
621 method_headers.insert(OatQuickMethodHeader::FromCodePointer(it->second.GetCode()));
929 FreeCode(it->second.GetCode());
1090 const void* code = method_header->GetCode();
1125 const void* code = method_header->GetCode();
1295 OatQuickMethodHeader::FromCodePointer(data.GetCode());
1321 if (!data->IsCompiled() || GetLiveBitmap()->Test(FromCodeToAllocation(data->GetCode()))) {
[all...] |
| /art/runtime/ |
| H A D | oat_quick_method_header.h | 96 const uint8_t* GetCode() const { function
|
| H A D | art_method.cc | 684 << " " << (uintptr_t)(method_header->GetCode() + method_header->GetCodeSize());
|
| /art/compiler/linker/arm64/ |
| H A D | relative_patcher_arm64.cc | 402 DCHECK_EQ(ip0.GetCode(), 16u);
404 Thread::ReadBarrierMarkEntryPointsOffset<kArm64PointerSize>(ip0.GetCode());
420 CheckValidReg(base_reg.GetCode());
423 CheckValidReg(holder_reg.GetCode());
456 CheckValidReg(base_reg.GetCode());
484 CheckValidReg(root_reg.GetCode());
|
| /art/oatdump/ |
| H A D | oatdump.cc | 1414 : method_header->GetCode() - oat_file_.Begin();
|