| /art/runtime/arch/mips/ |
| H A D | asm_support_mips.S | 72 from unaligned (mod-4-aligned) mem location disp(base) */
73 .macro LDu feven,fodd,disp,base,temp
74 l.s \feven, \disp(\base)
75 lw \temp, \disp+4(\base)
80 to unaligned (mod-4-aligned) mem location disp(base) */
81 .macro SDu feven,fodd,disp,base,temp
83 s.s \feven, \disp(\base)
84 sw \temp, \disp+4(\base)
99 .macro LDu feven,fodd,disp,base,temp
100 l.s \feven, \disp(\bas
[all...] |
| /art/compiler/linker/arm64/ |
| H A D | relative_patcher_arm64_test.cc | 227 uint32_t disp = target_offset - (adrp_offset & ~0xfffu); local
229 DCHECK_ALIGNED(disp, 1u << 2);
231 ((disp & 0xfffu) << (10 - 2)); // imm12 = ((disp & 0xfffu) >> 2) is at bit 10.
234 (disp & 0xfffu) << 10; // imm12 = (disp & 0xfffu) is at bit 10.
239 ((disp & 0x3000u) << (29 - 12)) | // immlo = ((disp & 0x3000u) >> 12) is at bit 29,
240 ((disp & 0xffffc000) >> (14 - 5)) | // immhi = (disp >> 1
[all...] |
| H A D | relative_patcher_arm64.cc | 218 uint32_t disp = target_offset - ((patch_offset - literal_offset + pc_insn_offset) & ~0xfffu); local
252 insn = PatchAdrp(insn, disp);
302 uint32_t imm12 = (disp & 0xfffu) >> shift;
358 uint32_t disp = target_offset - patch_offset; local
359 DCHECK((disp >> 20) == 0u || (disp >> 20) == 4095u); // 21-bit signed.
360 insn |= (disp << (5 - 2)) & 0x00ffffe0u; // Shift bits 2-20 to 5-23.
592 uint32_t Arm64RelativePatcher::PatchAdrp(uint32_t adrp, uint32_t disp) { argument
595 ((disp & 0x00003000u) << (29 - 12)) |
597 ((disp
[all...] |
| H A D | relative_patcher_arm64.h | 109 static uint32_t PatchAdrp(uint32_t adrp, uint32_t disp);
|
| /art/compiler/utils/x86/ |
| H A D | assembler_x86.h | 109 void SetDisp8(int8_t disp) { argument
111 encoding_[length_++] = static_cast<uint8_t>(disp);
114 void SetDisp32(int32_t disp) { argument
116 int disp_size = sizeof(disp);
117 memmove(&encoding_[length_], &disp, disp_size);
152 Address(Register base_in, int32_t disp) { argument
153 Init(base_in, disp);
156 Address(Register base_in, int32_t disp, AssemblerFixup *fixup) { argument
157 Init(base_in, disp);
161 Address(Register base_in, Offset disp) { argument
165 Address(Register base_in, FrameOffset disp) argument
170 Address(Register base_in, MemberOffset disp) argument
174 Address(Register index_in, ScaleFactor scale_in, int32_t disp) argument
181 Address(Register base_in, Register index_in, ScaleFactor scale_in, int32_t disp) argument
185 Address(Register base_in, Register index_in, ScaleFactor scale_in, int32_t disp, AssemblerFixup *fixup) argument
207 Init(Register base_in, int32_t disp) argument
222 Init(Register base_in, Register index_in, ScaleFactor scale_in, int32_t disp) argument
[all...] |
| /art/compiler/utils/x86_64/ |
| H A D | assembler_x86_64.h | 151 void SetDisp8(int8_t disp) { argument
153 encoding_[length_++] = static_cast<uint8_t>(disp);
156 void SetDisp32(int32_t disp) { argument
158 int disp_size = sizeof(disp);
159 memmove(&encoding_[length_], &disp, disp_size);
188 Address(CpuRegister base_in, int32_t disp) { argument
189 Init(base_in, disp);
192 Address(CpuRegister base_in, Offset disp) { argument
193 Init(base_in, disp.Int32Value());
196 Address(CpuRegister base_in, FrameOffset disp) { argument
201 Address(CpuRegister base_in, MemberOffset disp) argument
205 Init(CpuRegister base_in, int32_t disp) argument
227 Address(CpuRegister index_in, ScaleFactor scale_in, int32_t disp) argument
234 Address(CpuRegister base_in, CpuRegister index_in, ScaleFactor scale_in, int32_t disp) argument
[all...] |
| /art/compiler/linker/arm/ |
| H A D | relative_patcher_thumb2.cc | 171 uint32_t disp = target_offset - (patch_offset + kPcDisplacement); local
172 DCHECK((disp >> 20) == 0u || (disp >> 20) == 0xfffu); // 21-bit signed.
173 insn |= ((disp << (26 - 20)) & 0x04000000u) | // Shift bit 20 to 26, "S".
174 ((disp >> (19 - 11)) & 0x00000800u) | // Shift bit 19 to 13, "J1".
175 ((disp >> (18 - 13)) & 0x00002000u) | // Shift bit 18 to 11, "J2".
176 ((disp << (16 - 12)) & 0x003f0000u) | // Shift bits 12-17 to 16-25, "imm6".
177 ((disp >> (1 - 0)) & 0x000007ffu); // Shift bits 1-12 to 0-11, "imm11".
|