/art/compiler/utils/arm/ |
H A D | managed_register_arm.cc | 29 Register low = AsRegisterPairLow(); local 31 return ArmManagedRegister::FromCoreRegister(low).Overlaps(other) || 37 SRegister low = AsOverlappingDRegisterLow(); local 40 return (low == other_sreg) || (high == other_sreg); 54 int low; local 57 low = (r * 2) + kNumberOfCoreRegIds; // Return a SRegister. 60 low = (r - kNumberOfDRegIds) * 2; // Return a Register. 61 if (low > 6) { 63 low = 1; 66 return low; [all...] |
/art/tools/ahat/src/main/com/android/ahat/ |
H A D | HtmlEscaper.java | 27 int low = 0; 34 sb.append(text.substring(low, i)); 36 low = i + 1; 43 sb.append(text.substring(low));
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/art/compiler/utils/mips/ |
H A D | managed_register_mips.cc | 30 Register low = AsRegisterPairLow(); local 32 return MipsManagedRegister::FromCoreRegister(low).Overlaps(other) || 38 FRegister low = AsOverlappingDRegisterLow(); local 41 return (low == other_freg) || (high == other_freg); 55 int low; local 58 low = (r * 2) + kNumberOfCoreRegIds; // Return an FRegister. 61 low = (r - kNumberOfDRegIds) * 2 + 2; // Return a Register. 62 if (low >= 24) { 64 low = 5; 67 return low; [all...] |
/art/runtime/interpreter/mterp/mips/ |
H A D | op_const_wide.S | 2 FETCH(a0, 1) # a0 <- bbbb (low) 3 FETCH(a1, 2) # a1 <- BBBB (low middle) 5 INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb (low word)
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H A D | op_mul_long_2addr.S | 8 LOAD64(a0, a1, t0) # vAA.low / high 12 LOAD64(a2, a3, t1) # vBB.low / high 29 SET_VREG64_GOTO(v0, v1, rOBJ, t1) # vA/vA+1 <- v0(low)/v1(high)
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H A D | op_const.S | 3 FETCH(a0, 1) # a0 <- bbbb (low)
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H A D | op_const_string_jumbo.S | 3 FETCH(a0, 1) # a0 <- bbbb (low)
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H A D | op_const_wide_32.S | 2 FETCH(a0, 1) # a0 <- 0000bbbb (low)
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/art/runtime/interpreter/mterp/mips64/ |
H A D | op_goto_32.S | 11 lh rINST, 2(rPC) # rINST <- aaaa (low)
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H A D | op_const_wide.S | 3 lh a0, 2(rPC) # a0 <- bbbb (low) 4 lh a1, 4(rPC) # a1 <- BBBB (low middle)
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H A D | op_const.S | 3 lh a0, 2(rPC) # a0 <- bbbb (low)
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H A D | op_const_string_jumbo.S | 4 lh a0, 2(rPC) # a0 <- bbbb (low)
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H A D | op_const_wide_32.S | 3 lh a0, 2(rPC) # a0 <- bbbb (low)
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/art/compiler/utils/arm64/ |
H A D | managed_register_arm64.cc | 67 int low = RegNo(); local 69 low += kNumberOfXRegIds; 71 low += kNumberOfXRegIds + kNumberOfWRegIds + kNumberOfDRegIds; 73 return low;
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/art/compiler/utils/x86/ |
H A D | managed_register_x86.cc | 42 Register low; member in struct:art::x86::RegisterPairDescriptor 48 #define REGISTER_PAIR_ENUMERATION(low, high) { low##_##high, low, high }, 68 Register low = AsRegisterPairLow(); local 70 return X86ManagedRegister::FromCpuRegister(low).Overlaps(other) || 85 return kRegisterPairs[r].low;
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/art/compiler/utils/x86_64/ |
H A D | managed_register_x86_64.cc | 41 Register low; member in struct:art::x86_64::RegisterPairDescriptor 47 #define REGISTER_PAIR_ENUMERATION(low, high) { low##_##high, low, high }, 63 Register low = AsRegisterPairLow().AsRegister(); local 65 return X86_64ManagedRegister::FromCpuRegister(low).Overlaps(other) || 80 return kRegisterPairs[r].low;
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/art/runtime/interpreter/mterp/arm/ |
H A D | op_const_wide.S | 2 FETCH r0, 1 @ r0<- bbbb (low) 3 FETCH r1, 2 @ r1<- BBBB (low middle) 5 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word)
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H A D | op_const.S | 3 FETCH r0, 1 @ r0<- bbbb (low)
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H A D | op_const_string_jumbo.S | 3 FETCH r0, 1 @ r0<- bbbb (low)
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H A D | op_const_wide_32.S | 2 FETCH r0, 1 @ r0<- 0000bbbb (low)
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H A D | op_mul_long.S | 11 * The low word of the result holds ZX, the high word holds 13 * it doesn't fit in the low 64 bits. 31 add r2, r2, lr @ r2<- lr + low(ZxW + (YxX))
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H A D | op_mul_long_2addr.S | 21 add r2, r2, lr @ r2<- r2 + low(ZxW + (YxX))
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/art/runtime/interpreter/mterp/x86/ |
H A D | op_move_result_wide.S | 4 movl (%eax), %eax # Get low
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H A D | op_sget_wide.S | 18 SET_VREG %eax, rINST # fp[A]<- low part
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/art/compiler/optimizing/ |
H A D | common_arm.h | 86 int reg_code = location.low(); 220 inline Location LocationFrom(const vixl::aarch32::Register& low, argument 222 return Location::RegisterPairLocation(low.GetCode(), high.GetCode()); 225 inline Location LocationFrom(const vixl::aarch32::SRegister& low, argument 227 return Location::FpuRegisterPairLocation(low.GetCode(), high.GetCode());
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