Searched refs:reg (Results 1 - 25 of 145) sorted by relevance

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/art/compiler/utils/mips64/
H A Dmanaged_register_mips64_test.cc25 Mips64ManagedRegister reg = ManagedRegister::NoRegister().AsMips64(); local
26 EXPECT_TRUE(reg.IsNoRegister());
27 EXPECT_FALSE(reg.Overlaps(reg));
31 Mips64ManagedRegister reg = Mips64ManagedRegister::FromGpuRegister(ZERO); local
32 EXPECT_FALSE(reg.IsNoRegister());
33 EXPECT_TRUE(reg.IsGpuRegister());
34 EXPECT_FALSE(reg.IsFpuRegister());
35 EXPECT_FALSE(reg.IsVectorRegister());
36 EXPECT_EQ(ZERO, reg
110 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0); local
156 Mips64ManagedRegister reg = Mips64ManagedRegister::FromVectorRegister(W0); local
278 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0); local
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H A Dmanaged_register_mips64.h146 Mips64ManagedRegister reg(reg_id);
147 CHECK(reg.IsValidManagedRegister());
148 return reg;
152 std::ostream& operator<<(std::ostream& os, const Mips64ManagedRegister& reg);
157 mips64::Mips64ManagedRegister reg(id_);
158 CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister());
159 return reg;
/art/compiler/utils/arm/
H A Dmanaged_register_arm_test.cc25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); local
26 EXPECT_TRUE(reg.IsNoRegister());
27 EXPECT_TRUE(!reg.Overlaps(reg));
31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); local
32 EXPECT_TRUE(!reg.IsNoRegister());
33 EXPECT_TRUE(reg.IsCoreRegister());
34 EXPECT_TRUE(!reg.IsSRegister());
35 EXPECT_TRUE(!reg.IsDRegister());
36 EXPECT_TRUE(!reg
69 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); local
126 ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0); local
227 ArmManagedRegister reg = ArmManagedRegister::FromRegisterPair(R0_R1); local
459 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); local
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/art/compiler/utils/x86/
H A Dmanaged_register_x86_test.cc26 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); local
27 EXPECT_TRUE(reg.IsNoRegister());
28 EXPECT_TRUE(!reg.Overlaps(reg));
32 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); local
33 EXPECT_TRUE(!reg.IsNoRegister());
34 EXPECT_TRUE(reg.IsCpuRegister());
35 EXPECT_TRUE(!reg.IsXmmRegister());
36 EXPECT_TRUE(!reg.IsX87Register());
37 EXPECT_TRUE(!reg
66 X86ManagedRegister reg = X86ManagedRegister::FromXmmRegister(XMM0); local
92 X86ManagedRegister reg = X86ManagedRegister::FromX87Register(ST0); local
118 X86ManagedRegister reg = X86ManagedRegister::FromRegisterPair(EAX_EDX); local
256 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); local
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H A Dmanaged_register_x86.cc41 RegisterPair reg; // Used to verify that the enum is in sync. member in struct:art::x86::RegisterPairDescriptor
53 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { argument
54 if (reg == kNoRegisterPair) {
57 os << X86ManagedRegister::FromRegisterPair(reg);
84 CHECK_EQ(r, kRegisterPairs[r].reg);
93 CHECK_EQ(r, kRegisterPairs[r].reg);
114 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg) { argument
115 reg.Print(os);
/art/compiler/utils/x86_64/
H A Dmanaged_register_x86_64_test.cc25 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); local
26 EXPECT_TRUE(reg.IsNoRegister());
27 EXPECT_TRUE(!reg.Overlaps(reg));
31 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); local
32 EXPECT_TRUE(!reg.IsNoRegister());
33 EXPECT_TRUE(reg.IsCpuRegister());
34 EXPECT_TRUE(!reg.IsXmmRegister());
35 EXPECT_TRUE(!reg.IsX87Register());
36 EXPECT_TRUE(!reg
65 X86_64ManagedRegister reg = X86_64ManagedRegister::FromXmmRegister(XMM0); local
91 X86_64ManagedRegister reg = X86_64ManagedRegister::FromX87Register(ST0); local
117 X86_64ManagedRegister reg = X86_64ManagedRegister::FromRegisterPair(EAX_EDX); local
255 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); local
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/art/runtime/arch/arm/
H A Dcontext_arm.h53 bool IsAccessibleGPR(uint32_t reg) OVERRIDE {
54 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
55 return gprs_[reg] != nullptr;
58 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
59 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
60 return gprs_[reg];
63 uintptr_t GetGPR(uint32_t reg) OVERRIDE {
64 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
65 DCHECK(IsAccessibleGPR(reg));
66 return *gprs_[reg];
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/art/runtime/arch/arm64/
H A Dcontext_arm64.h53 bool IsAccessibleGPR(uint32_t reg) OVERRIDE {
54 DCHECK_LT(reg, arraysize(gprs_));
55 return gprs_[reg] != nullptr;
58 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
59 DCHECK_LT(reg, arraysize(gprs_));
60 return gprs_[reg];
63 uintptr_t GetGPR(uint32_t reg) OVERRIDE {
65 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfXRegisters));
66 DCHECK(IsAccessibleGPR(reg));
67 return *gprs_[reg];
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/art/runtime/arch/mips/
H A Dcontext_mips.h48 bool IsAccessibleGPR(uint32_t reg) OVERRIDE {
49 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
50 return gprs_[reg] != nullptr;
53 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
54 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
55 return gprs_[reg];
58 uintptr_t GetGPR(uint32_t reg) OVERRIDE {
59 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
60 DCHECK(IsAccessibleGPR(reg));
61 return *gprs_[reg];
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/art/runtime/arch/mips64/
H A Dcontext_mips64.h48 bool IsAccessibleGPR(uint32_t reg) OVERRIDE {
49 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters));
50 return gprs_[reg] != nullptr;
53 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
54 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters));
55 return gprs_[reg];
58 uintptr_t GetGPR(uint32_t reg) OVERRIDE {
59 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters));
60 DCHECK(IsAccessibleGPR(reg));
61 return *gprs_[reg];
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/art/runtime/arch/x86/
H A Dcontext_x86.h52 bool IsAccessibleGPR(uint32_t reg) OVERRIDE {
53 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
54 return gprs_[reg] != nullptr;
57 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
58 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
59 return gprs_[reg];
62 uintptr_t GetGPR(uint32_t reg) OVERRIDE {
63 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
64 DCHECK(IsAccessibleGPR(reg));
65 return *gprs_[reg];
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H A Dasm_support_x86.S76 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size
77 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg
78 #define CFI_RESTORE(reg) .cfi_restore reg
79 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size
88 #define CFI_DEF_CFA(reg,size)
89 #define CFI_DEF_CFA_REGISTER(reg)
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H A Dcontext_x86.cc77 void X86Context::SetGPR(uint32_t reg, uintptr_t value) { argument
78 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
79 DCHECK(IsAccessibleGPR(reg));
80 CHECK_NE(gprs_[reg], &gZero);
81 *gprs_[reg] = value;
84 void X86Context::SetFPR(uint32_t reg, uintptr_t value) { argument
85 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFloatRegisters));
86 DCHECK(IsAccessibleFPR(reg));
87 CHECK_NE(fprs_[reg], reinterpret_cast<const uint32_t*>(&gZero));
88 *fprs_[reg]
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/art/runtime/arch/x86_64/
H A Dcontext_x86_64.h52 bool IsAccessibleGPR(uint32_t reg) OVERRIDE {
53 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
54 return gprs_[reg] != nullptr;
57 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
58 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
59 return gprs_[reg];
62 uintptr_t GetGPR(uint32_t reg) OVERRIDE {
63 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
64 DCHECK(IsAccessibleGPR(reg));
65 return *gprs_[reg];
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H A Dasm_support_x86_64.S75 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size
76 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg
77 #define CFI_RESTORE(reg) .cfi_restore reg
78 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size
86 #define CFI_DEF_CFA(reg,size)
87 #define CFI_DEF_CFA_REGISTER(reg)
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/art/compiler/utils/arm64/
H A Dmanaged_register_arm64_test.cc27 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); local
28 EXPECT_TRUE(reg.IsNoRegister());
29 EXPECT_TRUE(!reg.Overlaps(reg));
34 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); local
36 EXPECT_TRUE(!reg.IsNoRegister());
37 EXPECT_TRUE(reg.IsXRegister());
38 EXPECT_TRUE(!reg.IsWRegister());
39 EXPECT_TRUE(!reg.IsDRegister());
40 EXPECT_TRUE(!reg
107 Arm64ManagedRegister reg = Arm64ManagedRegister::FromWRegister(W0); local
169 Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0); local
220 Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); local
376 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); local
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/art/compiler/debug/
H A Delf_debug_frame_writer.h45 for (int reg = 0; reg < 13; reg++) {
46 if (reg < 4 || reg == 12) {
47 opcodes.Undefined(Reg::ArmCore(reg));
49 opcodes.SameValue(Reg::ArmCore(reg));
53 for (int reg = 0; reg < 32; reg
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/art/runtime/interpreter/mterp/arm/
H A Dheader.S69 reg nick purpose
198 .macro FETCH_ADVANCE_INST_RB reg
199 ldrh rINST, [rPC, \reg]!
208 .macro FETCH reg, count
209 ldrh \reg, [rPC, #((\count)*2)]
212 .macro FETCH_S reg, count
213 ldrsh \reg, [rPC, #((\count)*2)]
221 .macro FETCH_B reg, count, byte
222 ldrb \reg, [rPC, #((\count)*2+(\byte))]
228 .macro GET_INST_OPCODE reg
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/art/test/404-optimizing-allocator/src/
H A DMain.java17 // Note that $opt$reg$ is a marker for the optimizing compiler to test
23 expectEquals(4, $opt$reg$TestLostCopy());
24 expectEquals(-10, $opt$reg$TestTwoLive());
25 expectEquals(-20, $opt$reg$TestThreeLive());
26 expectEquals(5, $opt$reg$TestFourLive());
27 expectEquals(10, $opt$reg$TestMultipleLive());
28 expectEquals(1, $opt$reg$TestWithBreakAndContinue());
29 expectEquals(-15, $opt$reg$testSpillInIf(5, 6, 7));
30 expectEquals(-567, $opt$reg$TestAgressiveLive1(1, 2, 3, 4, 5, 6, 7));
31 expectEquals(-77, $opt$reg
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/art/runtime/interpreter/mterp/arm64/
H A Dheader.S70 reg nick purpose
78 x16 ip scratch reg
79 x17 ip2 scratch reg (used by macros)
192 .macro FETCH_ADVANCE_INST_RB reg
193 add xPC, xPC, \reg, sxtw
203 .macro FETCH reg, count
204 ldrh \reg, [xPC, #((\count)*2)]
207 .macro FETCH_S reg, count
208 ldrsh \reg, [xPC, #((\count)*2)]
216 .macro FETCH_B reg, coun
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/art/runtime/interpreter/mterp/mips64/
H A Dheader.S80 reg nick purpose
167 .macro FETCH_ADVANCE_INST_RB reg
168 daddu rPC, rPC, \reg
197 .macro GET_INST_OPCODE reg
198 and \reg, rINST, 255
204 .macro GOTO_OPCODE reg
206 sll AT, \reg, 7
219 .macro GET_VREG reg, vreg
222 lw \reg, 0(AT)
225 .macro GET_VREG_U reg, vre
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/art/runtime/arch/
H A Dcontext.h65 virtual bool IsAccessibleGPR(uint32_t reg) = 0;
68 virtual uintptr_t* GetGPRAddress(uint32_t reg) = 0;
72 virtual uintptr_t GetGPR(uint32_t reg) = 0;
76 virtual void SetGPR(uint32_t reg, uintptr_t value) = 0;
79 virtual bool IsAccessibleFPR(uint32_t reg) = 0;
83 virtual uintptr_t GetFPR(uint32_t reg) = 0;
87 virtual void SetFPR(uint32_t reg, uintptr_t value) = 0;
/art/compiler/debug/dwarf/
H A Ddebug_frame_opcode_writer.h73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { argument
74 Offset(reg, offset - current_cfa_offset_);
117 void ALWAYS_INLINE Offset(Reg reg, int offset) { argument
122 if (0 <= reg.num() && reg.num() <= 0x3F) {
123 this->PushUint8(DW_CFA_offset | reg.num());
127 this->PushUleb128(reg.num());
133 this->PushUleb128(reg.num());
139 void ALWAYS_INLINE Restore(Reg reg) { argument
142 if (0 <= reg
151 Undefined(Reg reg) argument
159 SameValue(Reg reg) argument
168 Register(Reg reg, Reg new_reg) argument
191 DefCFA(Reg reg, int offset) argument
208 DefCFARegister(Reg reg) argument
234 ValOffset(Reg reg, int offset) argument
261 Expression(Reg reg, uint8_t* expr, int expr_size) argument
272 ValExpression(Reg reg, uint8_t* expr, int expr_size) argument
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/art/disassembler/
H A Ddisassembler_arm64.cc45 const CPURegister& reg) {
47 if (reg.IsRegister() && reg.Is64Bits()) {
48 if (reg.GetCode() == TR) {
51 } else if (reg.GetCode() == LR) {
58 Disassembler::AppendRegisterNameToOutput(instr, reg);
44 AppendRegisterNameToOutput(const Instruction* instr, const CPURegister& reg) argument
/art/runtime/interpreter/
H A Dshadow_frame.cc32 uint16_t reg = accessor.RegistersSize() - accessor.InsSize(); local
33 return GetVRegReference(reg);

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