Searched refs:BIT22 (Results 1 - 25 of 34) sorted by relevance

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/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
H A DSP804Timer.h55 #define SP810_SYS_CTRL_TIMER3_EN BIT22
/device/linaro/bootloader/edk2/OvmfPkg/Library/AcpiTimerLib/
H A DAcpiTimerLib.c46 Delay &= BIT22 - 1;
52 Delay = BIT22;
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/
H A DIntelPchAcpiTimerLib.c97 Delay &= BIT22 - 1;
103 Delay = BIT22;
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsPcie.h73 #define B_PCH_PCIE_SLCTL_SLSTS_PDS BIT22 // Presence Detect State
H A DPchRegsPcu.h422 #define B_PCH_ILB_DEF0_SHRTSYNC BIT22 // Short Sync Abort Defeature
684 #define B_PCH_PMC_PM_STS_PMC_MSG_3_FULL BIT22 // PMC 3 Message Full Status
755 #define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC2 BIT22 // PCI Express Function 2 Disable
787 #define B_PCH_PMC_PMIR_LTR_DEF BIT22 // LTR Default
806 #define B_PCH_PMC_GPI_ROUT_11 (BIT23 | BIT22)
880 #define B_PCH_PMC_D3_STS_0_PCIEF2 BIT22 // PCIe Function 2
917 #define B_PCH_PMC_D3_STDBY_STS_0_PCIEF2 BIT22 // PCIe Function 2
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
H A Dgeneral_definitions.h39 #undef BIT22 macro
75 #define BIT22 0x00400000U macro
H A Dmeminit.c538 isbM32m(DDRPHY, (DQOBSCKEBBCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), ((bl_grp_i) ? (0x00) : (BIT22)), (BIT22)); // Analog MUX select - IO2xCLKSEL
602 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
603 isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT_for_PM_MSG_gt0, MDLL Turn On
604 isbM32m(DDRPHY, (CMDPMDLYREG2 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // MPLL Divider Reset Delays
605 isbM32m(DDRPHY, (CMDPMDLYREG1 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn Off Delays: VREG, Staggered MDLL, MDLL, PI
606 isbM32m(DDRPHY, (CMDPMDLYREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: MPLL, Staggered MDLL, PI, IOBUFACT
607 isbM32m(DDRPHY, (CMDPMCONFIG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x6<<8)|BIT6|(0x4<<0)), (BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|(BIT11|BIT10|BIT9|BIT8)|BIT6|(BIT3|BIT2|BIT1|BIT0))); // Allow PUnit signals
837 isbM32m(DDRPHY, (CMDCLKALIGNREG1 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x18<<16)|(0x10<<8)|(0x8<<2)|(0x1<<0)), ((BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2)|(BIT1|BIT0))); // NUM_SAMPLES, MAX_SAMPLES, MACRO_PI_STEP, MICRO_PI_STEP
/device/linaro/bootloader/edk2/CorebootPayloadPkg/Library/AcpiTimerLib/
H A DAcpiTimerLib.c97 Delay &= BIT22 - 1;
103 Delay = BIT22;
/device/linaro/bootloader/edk2/MdePkg/Include/Library/
H A DSmbusLib.h34 ( ((Pec) ? BIT22: 0) | \
66 #define SMBUS_LIB_PEC(SmBusAddress) ((BOOLEAN) (((SmBusAddress) & BIT22) != 0))
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/
H A DBoardFeatures.h70 #define B_BOARD_FEATURES_MEMORY_SLOT_MASK BIT23 | BIT22
71 #define V_BOARD_FEATURES_1_MEMORY_SLOT 0 // BIT22=0, BIT23=0
72 #define V_BOARD_FEATURES_2_MEMORY_SLOT BIT22 // BIT22=1, BIT23=0
73 #define V_BOARD_FEATURES_3_MEMORY_SLOT BIT23 // BIT22=0, BIT23=1
74 #define V_BOARD_FEATURES_4_MEMORY_SLOT BIT23 | BIT22 // BIT22=1, BIT23=1
164 #define B_BOARD_FEATURES_MEMORY_TYPE_DDR3 BIT22
/device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/
H A DSataRegisters.h98 #define EFI_AHCI_PORT_IS_PRCS BIT22
170 #define EFI_AHCI_PORT_SERR_HE BIT22
/device/linaro/bootloader/edk2/PcAtChipsetPkg/Library/AcpiTimerLib/
H A DAcpiTimerLib.c160 Delay &= BIT22 - 1;
166 Delay = BIT22;
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/
H A DCommonIncludes.h94 #define BIT22 0x00400000
85 #define BIT22 macro
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
H A DOmap3530MMCHS.h120 #define DEB BIT22
133 #define DEB_EN BIT22
148 #define DEB_SIGEN BIT22
/device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
H A DPeImage.h316 #define EFI_IMAGE_SCN_ALIGN_8BYTES BIT22 ///< 0x00400000
317 #define EFI_IMAGE_SCN_ALIGN_16BYTES (BIT20|BIT22) ///< 0x00500000
318 #define EFI_IMAGE_SCN_ALIGN_32BYTES (BIT21|BIT22) ///< 0x00600000
319 #define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/
H A DPchRegs.h68 #define BIT22 0x00400000 macro
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/
H A DAhciMode.h106 #define EFI_AHCI_PORT_IS_PRCS BIT22
175 #define EFI_AHCI_PORT_SERR_HE BIT22
/device/linaro/bootloader/edk2/SecurityPkg/Tcg/Opal/OpalPasswordSmm/
H A DOpalAhciMode.h99 #define EFI_AHCI_PORT_IS_PRCS BIT22
168 #define EFI_AHCI_PORT_SERR_HE BIT22
/device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/
H A DBaseTypes.h243 #define BIT22 0x00400000 macro
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/
H A DArmDisassembler.c177 B = (OpCode & BIT22) == BIT22; // Also called S
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
H A DXhciReg.h179 #define XHC_PORTSC_PLC BIT22 // Port Link State Change
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/
H A DXhciReg.h94 #define XHC_PORTSC_PLC BIT22 // Port Link State Change
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
H A DIoh.h51 #define BIT22 0x00400000 macro
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/
H A DVlvCommonDefinitions.h99 #define BIT22 0x00400000 macro
/device/linaro/bootloader/edk2/MdePkg/Include/
H A DBase.h387 #define BIT22 0x00400000 macro

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