Searched refs:cpu_id (Results 1 - 20 of 20) sorted by relevance

/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/common/
H A Dplat_topology.c22 unsigned int cluster_id, cpu_id; local
24 cpu_id = mpidr & MPIDR_AFFLVL_MASK;
27 cpu_id += (cluster_id >> PLAT_RK_CLST_TO_CPUID_SHIFT);
29 if (cpu_id >= PLATFORM_CORE_COUNT)
32 return cpu_id;
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/
H A Dtegra_topology.c30 unsigned int cluster_id, cpu_id; local
33 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
39 * Validate cpu_id by checking whether it represents a CPU in
42 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
45 return (cpu_id + (cluster_id * 4));
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/
H A Dhikey_topology.c43 unsigned int cluster_id, cpu_id; local
51 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
57 * Validate cpu_id by checking whether it represents a CPU in
60 if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER)
63 return (cpu_id + (cluster_id * 4));
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/
H A Dhikey960_topology.c43 unsigned int cluster_id, cpu_id; local
51 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
57 * Validate cpu_id by checking whether it represents a CPU in
60 if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER)
63 return (cpu_id + (cluster_id * 4));
/device/linaro/bootloader/arm-trusted-firmware/plat/qemu/
H A Dtopology.c38 unsigned int cluster_id, cpu_id; local
45 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
50 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
/device/linaro/bootloader/arm-trusted-firmware/plat/socionext/uniphier/
H A Duniphier_topology.c29 unsigned int cluster_id, cpu_id; local
35 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
36 if (cpu_id >= UNIPHIER_MAX_CPUS_PER_CLUSTER)
/device/linaro/bootloader/arm-trusted-firmware/plat/xilinx/zynqmp/
H A Dplat_psci.c33 unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); local
37 if (cpu_id == -1)
41 mmio_write_32(APU_RVBAR_L_0 + (cpu_id << 3), zynqmp_sec_entry);
42 mmio_write_32(APU_RVBAR_H_0 + (cpu_id << 3), zynqmp_sec_entry >> 32);
46 r &= ~(1 << APU_CONFIG_0_VINITHI_SHIFT << cpu_id);
51 r &= ~(1 << cpu_id);
55 mmio_write_32(PMU_GLOBAL_REQ_PWRUP_EN, 1 << cpu_id);
56 mmio_write_32(PMU_GLOBAL_REQ_PWRUP_TRIG, 1 << cpu_id);
58 while (mmio_read_32(PMU_GLOBAL_REQ_PWRUP_STATUS) & (1 << cpu_id))
64 CRF_APB_RST_FPD_APU_ACPU_RESET) << cpu_id);
72 unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); local
91 unsigned int cpu_id = plat_my_core_pos(); local
108 unsigned int cpu_id = plat_my_core_pos(); local
132 unsigned int cpu_id = plat_my_core_pos(); local
159 unsigned int cpu_id = plat_my_core_pos(); local
192 unsigned int cpu_id = plat_my_core_pos(); local
209 unsigned int cpu_id = plat_my_core_pos(); local
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/device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/fvp/
H A Dfvp_topology.c59 unsigned int clus_id, cpu_id, thread_id; local
64 cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
68 cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
74 if (cpu_id >= FVP_MAX_CPUS_PER_CLUSTER)
/device/linaro/bootloader/arm-trusted-firmware/plat/arm/common/
H A Darm_topology.c18 unsigned int cluster_id, cpu_id; local
28 cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
33 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
43 /* Validate cpu_id by checking whether it represents a CPU in
45 if (cpu_id >= plat_arm_get_cluster_core_count(mpidr))
/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/
H A Dplat_topology.c63 unsigned int cluster_id, cpu_id; local
71 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
77 * Validate cpu_id by checking whether it represents a CPU in
80 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
83 return (cpu_id + (cluster_id * 4));
H A Dplat_pm.c314 unsigned long cpu_id; local
325 cpu_id = mpidr & MPIDR_CPU_MASK;
329 rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
331 rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
335 cluster_id, cpu_id, mmio_read_32(rv));
347 unsigned long cpu_id; local
351 cpu_id = mpidr & MPIDR_CPU_MASK;
355 rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
357 rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
361 cluster_id, cpu_id, mmio_read_3
443 unsigned long cpu_id; local
485 unsigned long cpu_id; local
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/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/common/drivers/pmu/
H A Dpmu_com.h80 static int check_cpu_wfie(uint32_t cpu_id, uint32_t wfie_msk) argument
84 if (cpu_id >= PLATFORM_CLUSTER0_CORE_COUNT) {
86 cpu_id -= PLATFORM_CLUSTER0_CORE_COUNT;
92 wfie_msk <<= (clstb_cpu_wfe + cpu_id);
94 wfie_msk <<= (clstl_cpu_wfe + cpu_id);
104 cluster_id, cpu_id, wfie_msk);
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/flowctrl/
H A Dflowctrl.c44 static inline void tegra_fc_cc4_ctrl(int cpu_id, uint32_t val) argument
46 mmio_write_32(flowctrl_offset_cc4_ctrl[cpu_id], val);
47 val = mmio_read_32(flowctrl_offset_cc4_ctrl[cpu_id]);
50 static inline void tegra_fc_cpu_csr(int cpu_id, uint32_t val) argument
52 mmio_write_32(flowctrl_offset_cpu_csr[cpu_id], val);
53 val = mmio_read_32(flowctrl_offset_cpu_csr[cpu_id]);
56 static inline void tegra_fc_halt_cpu(int cpu_id, uint32_t val) argument
58 mmio_write_32(flowctrl_offset_halt_cpu[cpu_id], val);
59 val = mmio_read_32(flowctrl_offset_halt_cpu[cpu_id]);
62 static void tegra_fc_prepare_suspend(int cpu_id, uint32_ argument
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/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c33 static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) argument
37 pd_reg = mmio_read_32(PMU_BASE + PMU_PWRDN_CON) & BIT(cpu_id);
38 apm_reg = mmio_read_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id)) &
51 static int cpus_power_domain_on(uint32_t cpu_id) argument
55 cpu_pd = PD_CPU0 + cpu_id;
56 cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id);
60 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
65 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
72 WARN("%s: cpu%d is not in off,!\n", __func__, cpu_id);
76 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
83 cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) argument
135 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); local
150 uint32_t cpu_id = plat_my_core_pos(); local
159 uint32_t cpu_id = plat_my_core_pos(); local
174 uint32_t cpu_id = plat_my_core_pos(); local
183 uint32_t cpu_id = plat_my_core_pos(); local
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/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt6795/
H A Dplat_pm.c240 unsigned long cpu_id; local
251 cpu_id = mpidr & MPIDR_CPU_MASK;
255 rv = (uintptr_t)&mt6795_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
257 rv = (uintptr_t)&mt6795_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
261 cluster_id, cpu_id, mmio_read_32(rv));
317 unsigned long cpu_id; local
324 cpu_id = mpidr & MPIDR_CPU_MASK;
328 rv = (uintptr_t)&mt6795_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
330 rv = (uintptr_t)&mt6795_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/
H A Dpmu.c444 static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) argument
446 assert(cpu_id < PLATFORM_CORE_COUNT);
447 return core_pm_cfg_info[cpu_id];
450 static inline void set_cpus_pwr_domain_cfg_info(uint32_t cpu_id, uint32_t value) argument
452 assert(cpu_id < PLATFORM_CORE_COUNT);
453 core_pm_cfg_info[cpu_id] = value;
455 flush_dcache_range((uintptr_t)&core_pm_cfg_info[cpu_id],
460 static int cpus_power_domain_on(uint32_t cpu_id) argument
463 uint32_t cpu_pd = PD_CPUL0 + cpu_id;
472 cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id);
499 cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) argument
534 uint32_t cpu_id = plat_my_core_pos(); local
578 uint32_t cpu_id = plat_my_core_pos(); local
618 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); local
633 uint32_t cpu_id = plat_my_core_pos(); local
656 uint32_t cpu_id = plat_my_core_pos(); local
684 uint32_t cpu_id = plat_my_core_pos(); local
707 uint32_t cpu_id = plat_my_core_pos(); local
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/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
H A Dplat_setup.c249 unsigned int cluster_id, cpu_id, pos; local
252 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
262 * Validate cpu_id by checking whether it represents a CPU in
265 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
269 pos = cpu_id + (cluster_id << 2);
/device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/
H A DCTA15-A7Helper.asm48 // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48
49 // with cpu_id[0:3] and cluster_id[4:7]
79 // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48
80 // with cpu_id[0:3] and cluster_id[4:7]
/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/
H A Dspm_mcdi.c406 unsigned long cpu_id = mpidr & MPIDR_CPU_MASK; local
414 if (i == cpu_id)
424 if (i == cpu_id)
/device/linaro/bootloader/edk2/StdLib/Include/Arm/machine/
H A Dcpufunc.h157 #define cpu_id() cpufuncs.cf_id() macro

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