Searched refs:tCL (Results 1 - 6 of 6) sorted by relevance

/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
H A Dmrc.h78 // tCL is DRAM CAS Latency in clocks.
83 uint8_t tCL; // CAS latency in clocks member in struct:DRAMParams_s
H A Dgen5_iosf_sb_definitions.h82 uint32_t tCL :3; /**< bit [14:12] CAS Latency */ member in struct:__anon10007::__anon10008
H A Dmeminit.c415 TCL = mrc_params->params.tCL; // CAS latency in clocks
430 Dtr0.field.tCL = TCL - 5; //Convert from TCL (DRAM clocks) to VLV indx
473 Dtr4.field.RDODTSTRT = Dtr1.field.tCMD + Dtr0.field.tCL - Dtr1.field.tWCL + 2; //Convert from WL (DRAM clocks) to VLV indx
474 Dtr4.field.RDODTSTOP = Dtr1.field.tCMD + Dtr0.field.tCL - Dtr1.field.tWCL + 2;
506 tCAS = mrc_params->params.tCL;
1036 mrs0Command.field.casLatency = DTR0reg.field.tCL + 1;
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
H A DDdrMemoryController.h184 unsigned tCL :2; /**< CAS Latency (3,4,5,6) */ member in struct:__anon9983::__anon9984
/device/linaro/bootloader/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/
H A DMrcWrapper.h123 UINT8 tCL; ///< DRAM CAS Latency in clocks. member in struct:__anon9967
H A DMrcWrapper.c133 MrcData->params.tCL = ItemData->tCL;
152 DEBUG ((EFI_D_INFO, "MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n",
154 MrcData->params.tCL,

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