Searched refs:AddrIdx (Results 1 - 4 of 4) sorted by relevance
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCNaCl.h | 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
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| H A D | MipsNaClELFStreamer.cpp | 116 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, argument
122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
149 unsigned AddrIdx; variable
151 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx,
156 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx)
162 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter);
202 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, argument
223 *AddrIdx = 1;
234 *AddrIdx = 1;
242 *AddrIdx
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 171 int AddrIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::addr); local
172 const MachineOperand &AddrReg0 = I->getOperand(AddrIdx);
173 const MachineOperand &AddrReg1 = MBBI->getOperand(AddrIdx);
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsDelaySlotFiller.cpp | 685 unsigned AddrIdx; local
686 if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) &&
687 baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||
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