Searched refs:BITFIELD64_RANGE (Results 1 - 7 of 7) sorted by relevance
| /external/mesa3d/src/compiler/ |
| H A D | shader_enums.h | 162 #define VERT_BIT_ALL BITFIELD64_RANGE(0, VERT_ATTRIB_MAX)
165 #define VERT_BIT_FF_ALL BITFIELD64_RANGE(0, VERT_ATTRIB_FF_MAX)
168 BITFIELD64_RANGE(VERT_ATTRIB_TEX(0), VERT_ATTRIB_TEX_MAX)
172 BITFIELD64_RANGE(VERT_ATTRIB_GENERIC(0), VERT_ATTRIB_GENERIC_MAX)
282 #define VARYING_BITS_TEX_ANY BITFIELD64_RANGE(VARYING_SLOT_TEX0, \
|
| /external/mesa3d/src/mesa/swrast_setup/ |
| H A D | ss_context.c | 146 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))
157 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_GENERIC0, _TNL_NUM_GENERIC)) {
|
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| H A D | r200_swtcl.c | 102 (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) ) {
162 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
257 if ((0 == (tnl->render_inputs_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)))
263 if (tnl->render_inputs_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
|
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| H A D | radeon_swtcl.c | 113 (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) {
176 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
296 (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)
|
| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| H A D | i830_vtbl.c | 96 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
127 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| H A D | brw_context.h | 346 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
|
| /external/mesa3d/src/mesa/main/ |
| H A D | mtypes.h | 69 #define BITFIELD64_RANGE(b, count) \ macro
|
Completed in 234 milliseconds