Searched refs:Bitcast (Results 1 - 23 of 23) sorted by relevance

/external/swiftshader/third_party/LLVM/include/llvm/MC/
H A DMCInstrDesc.h109 Bitcast, enumerator in enum:llvm::MCID::__anon22460
375 return Flags & (1 << MCID::Bitcast);
/external/llvm/include/llvm/MC/
H A DMCInstrDesc.h109 Bitcast, enumerator in enum:llvm::MCID::Flag
274 bool isBitcast() const { return Flags & (1 << MCID::Bitcast); }
/external/llvm/lib/Transforms/Vectorize/
H A DLoadStoreVectorizer.cpp806 Value *Bitcast = local
808 StoreInst *SI = cast<StoreInst>(Builder.CreateStore(Vec, Bitcast));
928 Value *Bitcast = local
931 LoadInst *LI = cast<LoadInst>(Builder.CreateLoad(Bitcast));
938 InstrsToReorder.push_back(cast<Instruction>(Bitcast));
965 InstrsToReorder.push_back(cast<Instruction>(Bitcast));
/external/tensorflow/tensorflow/compiler/xla/service/
H A Dwhile_loop_invariant_code_motion_test.cc324 Contains(op::Bitcast()));
373 Each(Not(op::Bitcast())));
375 EXPECT_THAT(entry_computation->instructions(), Contains(op::Bitcast()));
H A Dhlo_matchers.h102 HLO_MATCHER(Bitcast);
H A Dhlo_alias_analysis_test.cc805 TEST_F(HloAliasAnalysisTest, Bitcast) {
H A Dalgebraic_simplifier_test.cc1284 op::Tuple(op::Bitcast(), dimensions_wrong_reshape, layout_wrong_reshape));
1410 EXPECT_THAT(computation->root_instruction(), op::Bitcast(param));
1436 EXPECT_THAT(computation->root_instruction(), op::Bitcast(param));
/external/spirv-llvm/lib/SPIRV/libSPIRV/
H A DSPIRVOpCodeEnum.h115 _SPIRV_OP(Bitcast, 124)
H A DSPIRVInstruction.h1094 _SPIRV_OP(Bitcast)
/external/llvm/include/llvm/CodeGen/
H A DMachineInstr.h510 return hasProperty(MCID::Bitcast, Type);
/external/swiftshader/third_party/subzero/src/
H A DWasmTranslator.cpp873 InstCast::create(Func, InstCast::Bitcast, Dest, Input));
878 InstCast::create(Func, InstCast::Bitcast, Dest, Input));
883 InstCast::create(Func, InstCast::Bitcast, Dest, Input));
918 InstCast::create(Func, InstCast::Bitcast, Dest, Input));
H A DIceConverter.cpp275 Ice::InstCast::Bitcast);
H A DIceCfg.cpp1158 // Check that it's a Cast instruction with a Bitcast operation.
1160 if (Cast == nullptr || Cast->getCastKind() != InstCast::Bitcast)
1178 /// variable, or the same for a pointer-type InstCast::Bitcast, or when an
1180 /// Note that InstAssignment instructions and pointer-type InstCast::Bitcast
H A DPNaClTranslator.cpp1924 CastKind = Ice::InstCast::Bitcast;
1964 CastKind = Ice::InstCast::Bitcast;
H A DIceTargetLoweringX86BaseImpl.h3107 case InstCast::Bitcast: {
3116 llvm_unreachable("Unexpected Bitcast dest type");
3224 // Bitcast requires equal type sizes, which isn't strictly the case
4122 auto *Cast = InstCast::create(Func, InstCast::Bitcast, Dest, T);
4166 auto *Cast = InstCast::create(Func, InstCast::Bitcast, T, Value);
7493 case InstCast::Bitcast: {
H A DIceTargetLoweringMIPS32.cpp508 case InstCast::Bitcast: {
3832 case InstCast::Bitcast: {
3841 "Bitcast: vector type should have been prelowered.");
H A DIceTargetLoweringARM32.cpp649 case InstCast::Bitcast: {
4146 case InstCast::Bitcast: {
/external/tensorflow/tensorflow/core/grappler/optimizers/
H A Darithmetic_optimizer_test.cc1110 Output bc1 = ops::Bitcast(s, inputs, DT_QINT8);
1111 Output bc2 = ops::Bitcast(s, bc1, DT_INT8);
1125 [](const NodeDef& node) { return node.op() == "Bitcast"; }));
1131 Output bc1 = ops::Bitcast(s, inputs, DT_QINT8);
1132 Output bc2 = ops::Bitcast(s, bc1, DT_INT8);
1145 [](const NodeDef& node) { return node.op() == "Bitcast"; }));
/external/spirv-llvm/lib/SPIRV/
H A DSPIRVInternal.h102 _SPIRV_OP(BitCast, Bitcast)
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86GenInstrInfo.inc5434 { 1250, 2, 1, 0, 0, "MMX_MOVD64from64rr", 0|(1<<MCID::Bitcast), 0xfc002103ULL, NULL, NULL, OperandInfo150 }, // Inst #1250 = MMX_MOVD64from64rr
5439 { 1255, 2, 1, 0, 0, "MMX_MOVD64rrv164", 0|(1<<MCID::Bitcast), 0xdc002105ULL, NULL, NULL, OperandInfo154 }, // Inst #1255 = MMX_MOVD64rrv164
5659 { 1475, 2, 1, 0, 0, "MOV64toSDrr", 0|(1<<MCID::Bitcast), 0xdd002145ULL, NULL, NULL, OperandInfo102 }, // Inst #1475 = MOV64toSDrr
5691 { 1507, 2, 1, 0, 0, "MOVDI2SSrr", 0|(1<<MCID::Bitcast), 0xdd000145ULL, NULL, NULL, OperandInfo105 }, // Inst #1507 = MOVDI2SSrr
5737 { 1553, 2, 1, 0, 0, "MOVSDto64rr", 0|(1<<MCID::Bitcast), 0xfd002143ULL, NULL, NULL, OperandInfo109 }, // Inst #1553 = MOVSDto64rr
5744 { 1560, 2, 1, 0, 0, "MOVSS2DIrr", 0|(1<<MCID::Bitcast), 0xfd000143ULL, NULL, NULL, OperandInfo108 }, // Inst #1560 = MOVSS2DIrr
7312 { 3128, 2, 1, 0, 0, "VMOV64toSDrr", 0|(1<<MCID::Bitcast), 0x6dd000145ULL, NULL, NULL, OperandInfo102 }, // Inst #3128 = VMOV64toSDrr
7336 { 3152, 2, 1, 0, 0, "VMOVDI2SSrr", 0|(1<<MCID::Bitcast), 0x2dd000145ULL, NULL, NULL, OperandInfo105 }, // Inst #3152 = VMOVDI2SSrr
7400 { 3216, 2, 1, 0, 0, "VMOVSDto64rr", 0|(1<<MCID::Bitcast), 0x4fd000143ULL, NULL, NULL, OperandInfo109 }, // Inst #3216 = VMOVSDto64rr
7410 { 3226, 2, 1, 0, 0, "VMOVSS2DIrr", 0|(1<<MCID::Bitcast),
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/external/swiftshader/src/Reactor/
H A DSubzeroReactor.cpp858 auto bitcast = Ice::InstCast::create(::function, Ice::InstCast::Bitcast, result, vector.loadValue());
871 auto bitcast = Ice::InstCast::create(::function, Ice::InstCast::Bitcast, result, vector.loadValue());
906 auto bitcast = Ice::InstCast::create(::function, Ice::InstCast::Bitcast, vector, value);
918 auto bitcast = Ice::InstCast::create(::function, Ice::InstCast::Bitcast, vector, value);
1064 return createCast(Ice::InstCast::Bitcast, v, destType);
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp10706 SDNode *Bitcast = *Trunc->use_begin();
10709 if (Bitcast->getOpcode() != ISD::BITCAST ||
10710 Bitcast->getValueType(0) != MVT::f32)
10717 std::swap(Bitcast, Bitcast2);
10719 // Bitcast has the second float (in memory-layout order) and Bitcast2
10751 DCI.CombineTo(Bitcast, FloatLoad2);
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4298 // Bitcast operand 1 to i32.
4747 /// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
4765 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0)); local
4766 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
9816 // Bitcast an i64 load inserted into a vector to f64.
10069 // stored value. Bitcast it to the aligned type.
10085 // value. Bitcast it to the expected result type.
10297 // Bitcast the original vector into a vector of store-size units
10351 // Bitcast an i64 store extracted from a vector to f64.

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