/external/clang/test/SemaTemplate/ |
H A D | value-dependent-null-pointer-constant.cpp | 5 const char *f0(bool Cond) { argument 6 return Cond? "honk" : N; 9 const char *f1(bool Cond) { argument 10 return Cond? N : "honk";
|
/external/swiftshader/third_party/subzero/src/ |
H A D | IceAssemblerARM32.h | 181 bool SetFlags, CondARM32::Cond Cond); 184 bool SetFlags, CondARM32::Cond Cond); 187 bool SetFlags, CondARM32::Cond Cond); 190 bool SetFlags, CondARM32::Cond Cond); 192 void b(Label *L, CondARM32::Cond Cond); 219 ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, const TargetLowering *Lowering) argument 228 ldrex(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, const TargetLowering *Lowering) argument 291 str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, const TargetLowering *Lowering) argument 300 strex(const Operand *OpRd, const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, const TargetLowering *Lowering) argument 428 vldrd(const Operand *OpDd, const Operand *OpAddress, CondARM32::Cond Cond, const TargetLowering *Lowering) argument 437 vldrs(const Operand *OpSd, const Operand *OpAddress, CondARM32::Cond Cond, const TargetLowering *Lowering) argument 446 vldrq(const Operand *OpQd, const Operand *OpAddress, CondARM32::Cond Cond, const TargetLowering *Lowering) argument 600 vstrd(const Operand *OpDd, const Operand *OpAddress, CondARM32::Cond Cond, const TargetLowering *Lowering) argument 609 vstrs(const Operand *OpSd, const Operand *OpAddress, CondARM32::Cond Cond, const TargetLowering *Lowering) argument 618 vstrq(const Operand *OpQd, const Operand *OpAddress, CondARM32::Cond Cond, const TargetLowering *Lowering) argument [all...] |
H A D | IceConditionCodesARM32.h | 31 enum Cond { enum in class:Ice::CondARM32 37 static bool isDefined(Cond C) { return C != kNone; } 39 static bool isUnconditional(Cond C) { return !isDefined(C) || C == AL; }
|
H A D | IceConditionCodesMIPS32.h | 31 enum Cond { enum in class:Ice::CondMIPS32 37 static bool isDefined(Cond C) { return C != kNone; } 39 static bool isUnconditional(Cond C) { return !isDefined(C) || C == AL; }
|
H A D | IceAssemblerARM32.cpp | 143 IValueT encodeCondition(CondARM32::Cond Cond) { argument 144 return static_cast<IValueT>(Cond); 673 // cccc00110T00iiiiddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, 709 // cccc101liiiiiiiiiiiiiiiiiiiiiiii where cccc=Cond, l=Link, and 794 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT InstType, 806 assert(CondARM32::isDefined(Cond)); 807 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | 814 void AssemblerARM32::emitType01(CondARM32::Cond Con [all...] |
/external/deqp/framework/delibs/decpp/ |
H A D | deMeta.hpp | 33 template <typename T, bool Cond> 42 template <bool Cond> 47 Value = !Cond
|
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
H A D | MBlazeInstrInfo.cpp | 118 SmallVectorImpl<MachineOperand> &Cond, 146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); 147 Cond.push_back(LastInst->getOperand(0)); 165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); 166 Cond.push_back(SecondLastInst->getOperand(0)); 189 const SmallVectorImpl<MachineOperand> &Cond, 193 assert((Cond.size() == 2 || Cond.size() == 0) && 197 if (!Cond.empty()) 198 Opc = (unsigned)Cond[ 115 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 187 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyInstrInfo.cpp | 98 SmallVectorImpl<MachineOperand> &Cond, 112 Cond.push_back(MachineOperand::CreateImm(true)); 113 Cond.push_back(MI.getOperand(1)); 123 Cond.push_back(MachineOperand::CreateImm(false)); 124 Cond.push_back(MI.getOperand(1)); 167 ArrayRef<MachineOperand> Cond, 169 if (Cond.empty()) { 177 assert(Cond.size() == 2 && "Expected a flag and a successor block"); 179 if (Cond[0].getImm()) { 180 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).addOperand(Cond[ 95 analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool ) const argument 164 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL) const argument [all...] |
H A D | WebAssemblyInstrInfo.h | 49 SmallVectorImpl<MachineOperand> &Cond, 53 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 56 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
/external/python/cpython2/Misc/ |
H A D | valgrind-python.supp | 39 Memcheck:Cond 153 ### Memcheck:Cond 183 ### Memcheck:Cond 204 Memcheck:Cond 237 Memcheck:Cond 247 Memcheck:Cond 268 Memcheck:Cond 292 ### Memcheck:Cond 303 ### Memcheck:Cond 318 Memcheck:Cond [all...] |
/external/libxcam/xcore/ |
H A D | xcam_mutex.h | 31 friend class Cond; 66 class Cond { class in namespace:XCam 68 XCAM_DEAD_COPY (Cond); 71 Cond () { function in class:XCam::Cond 74 ~Cond () {
|
/external/spirv-llvm/lib/SPIRV/libSPIRV/ |
H A D | SPIRVError.h | 103 SPIRVErrorLog::checkError(bool Cond, SPIRVErrorCode ErrCode, argument 107 if (Cond) 108 return Cond; 111 return Cond; 121 return Cond;
|
/external/swiftshader/third_party/subzero/crosstest/ |
H A D | test_select_main.cpp | 45 TyI1 Cond; local 48 setElement(Cond, j, Index() % 2); 52 Ty ResultLlc = select(Cond, Value1, Value2); 53 Ty ResultSz = Subzero_::select(Cond, Value1, Value2); 59 std::cout << "select<" << Vectors<T>::TypeName << ">(Cond="; 60 std::cout << vectAsString<TI1>(Cond) 81 v4si32 Cond; local 84 setElement(Cond, j, Index() % 2); 88 v4f32 ResultLlc = select(Cond, Value1, Value2); 89 v4f32 ResultSz = Subzero_::select(Cond, Value 111 Ty Cond; local [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_emulate_loops.c | 200 if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[0].File, 201 loop->Cond->U.I.SrcReg[0].Index)){ 202 limit = &loop->Cond->U.I.SrcReg[0]; 203 counter = &loop->Cond->U.I.SrcReg[1]; 205 else if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[1].File, 206 loop->Cond->U.I.SrcReg[1].Index)){ 207 limit = &loop->Cond->U.I.SrcReg[1]; 208 counter = &loop->Cond->U.I.SrcReg[0]; 286 switch(loop->Cond->U.I.Opcode){ 310 rc_remove_instruction(loop->Cond); [all...] |
H A D | radeon_emulate_loops.h | 37 struct rc_instruction * Cond; member in struct:loop_info
|
/external/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 73 SmallVectorImpl<MachineOperand> &Cond) const { 80 Cond.push_back(MachineOperand::CreateImm(Opc)); 83 Cond.push_back(Inst->getOperand(i)); 89 SmallVectorImpl<MachineOperand> &Cond, 92 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); 99 ArrayRef<MachineOperand> Cond) const { 100 unsigned Opc = Cond[0].getImm(); 104 for (unsigned i = 1; i < Cond.size(); ++i) { 105 if (Cond[i].isReg()) 106 MIB.addReg(Cond[ 86 analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 115 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL) const argument 179 analyzeBranch( MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, SmallVectorImpl<MachineInstr *> &BranchInstrs) const argument [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 189 SmallVectorImpl<MachineOperand> &Cond, 222 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 223 Cond.push_back(LastInst->getOperand(0)); 244 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 245 Cond.push_back(SecondLastInst->getOperand(0)); 277 const SmallVectorImpl<MachineOperand> &Cond, 281 assert((Cond.size() == 2 || Cond.size() == 0) && 285 if (Cond.empty()) { 290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[ 187 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 275 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
/external/clang/test/SemaCXX/ |
H A D | vector.cpp | 43 void conditional(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, argument 46 __typeof__(Cond? c16 : c16) *c16p1 = &c16; 47 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16; 48 __typeof__(Cond? c16e : c16e) *c16ep1 = &c16e; 49 __typeof__(Cond? ll16e : ll16e) *ll16ep1 = &ll16e; 52 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e; 53 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e; 54 __typeof__(Cond? ll16 : ll16e) *ll16ep2 = &ll16e; 55 __typeof__(Cond? ll16e : ll16) *ll16ep3 = &ll16e; 58 (void)(Cond 114 test_implicit_conversions(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, longlong16_e ll16e, convertible_to<char16> to_c16, convertible_to<longlong16> to_ll16, convertible_to<char16_e> to_c16e, convertible_to<longlong16_e> to_ll16e, convertible_to<char16&> rto_c16, convertible_to<char16_e&> rto_c16e) argument [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
H A D | AlphaInstrInfo.cpp | 90 const SmallVectorImpl<MachineOperand> &Cond, 93 assert((Cond.size() == 2 || Cond.size() == 0) && 98 if (Cond.empty()) // Unconditional branch 101 if (isAlphaIntCondCode(Cond[0].getImm())) 103 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 106 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 111 if (isAlphaIntCondCode(Cond[ 87 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument 218 AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument [all...] |
H A D | AlphaInstrInfo.h | 43 const SmallVectorImpl<MachineOperand> &Cond, 63 SmallVectorImpl<MachineOperand> &Cond, 68 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
/external/python/cpython3/Misc/ |
H A D | valgrind-python.supp | 39 Memcheck:Cond 153 ### Memcheck:Cond 183 ### Memcheck:Cond 204 Memcheck:Cond 237 Memcheck:Cond 247 Memcheck:Cond 268 Memcheck:Cond 292 ### Memcheck:Cond 303 ### Memcheck:Cond 317 Memcheck:Cond [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.h | 75 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 79 SmallVectorImpl<MachineOperand> &Cond, 84 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.h | 70 SmallVectorImpl<MachineOperand> &Cond, 76 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 80 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.h | 55 SmallVectorImpl<MachineOperand> &Cond, 59 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 81 SmallVectorImpl<MachineOperand> &Cond) const override;
|
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPUInstrInfo.h | 68 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 72 SmallVectorImpl<MachineOperand> &Cond, 79 const SmallVectorImpl<MachineOperand> &Cond,
|