Searched refs:DSLL32 (Results 1 - 10 of 10) sorted by relevance
| /external/pcre/dist2/src/sljit/ |
| H A D | sljitNativeMIPS_64.c | 85 ins = (shift == 32) ? DSLL32 : DSLL;
178 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(24), DR(dst)));
192 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(16), DR(dst)));
203 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(0), DR(dst)));
284 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1)));
360 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1)));
423 EMIT_SHIFT(DSLL, DSLL32, SLL, DSLLV, SLLV);
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| H A D | sljitNativeMIPS_common.c | 131 #define DSLL32 (HI(0) | LO(60)) macro
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| /external/valgrind/none/tests/mips64/ |
| H A D | shift_instructions.c | 7 DSLL32, DSLLV, DSRA, DSRA32, enumerator in enum:__anon29714
67 case DSLL32:
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| /external/v8/src/mips64/ |
| H A D | constants-mips64.h | 458 DSLL32 = ((7U << 3) + 4),
964 FunctionFieldToBitNumber(DSLL) | FunctionFieldToBitNumber(DSLL32) |
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| H A D | assembler-mips64.cc | 1908 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSLL32);
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| H A D | simulator-mips64.cc | 3578 case DSLL32:
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2499 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI);
3111 TOut.emitRRI(Mips::DSLL32, ATReg, ATReg, 0x1f, IDLoc, STI);
3633 FirstShift = Mips::DSLL32;
3637 FirstShift = Mips::DSLL32;
3644 SecondShift = Mips::DSLL32;
3648 SecondShift = Mips::DSLL32;
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCCodeEmitter.cpp | 70 Inst.setOpcode(Mips::DSLL32);
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| H A D | MipsTargetStreamer.cpp | 203 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
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| /external/capstone/arch/Mips/ |
| H A D | MipsGenAsmWriter.inc | 634 1107312817U, // DSLL32
2348 0U, // DSLL32
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