Searched refs:DSRL32 (Results 1 - 9 of 9) sorted by relevance
/external/pcre/dist2/src/sljit/ |
H A D | sljitNativeMIPS_64.c | 204 return push_inst(compiler, DSRL32 | T(dst) | D(dst) | SH_IMM(0), DR(dst)); 227 FAIL_IF(push_inst(compiler, SELECT_OP(DSRL32, SRL) | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_FLAG)); 287 return push_inst(compiler, SELECT_OP(DSRL32, SLL) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG); 363 return push_inst(compiler, SELECT_OP(DSRL32, SRL) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG); 427 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV);
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H A D | sljitNativeMIPS_common.c | 137 #define DSRL32 (HI(0) | LO(62)) macro
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/external/valgrind/none/tests/mips64/ |
H A D | shift_instructions.c | 8 DSRAV, DSRL, DSRL32, DSRLV, enumerator in enum:__anon29714 125 case DSRL32:
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/external/v8/src/mips64/ |
H A D | constants-mips64.h | 459 DSRL32 = ((7U << 3) + 6), 966 FunctionFieldToBitNumber(DSRL32) | FunctionFieldToBitNumber(SRA) |
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H A D | assembler-mips64.cc | 1885 (rd.code() << kRdShift) | (sa << kSaShift) | DSRL32; 1913 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRL32);
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H A D | simulator-mips64.cc | 3615 case DSRL32:
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 73 Inst.setOpcode(Mips::DSRL32);
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/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 2228 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); 3630 SecondShift = Mips::DSRL32; 3634 SecondShift = Mips::DSRL32; 3647 FirstShift = Mips::DSRL32; 3651 FirstShift = Mips::DSRL32;
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/external/capstone/arch/Mips/ |
H A D | MipsGenAsmWriter.inc | 641 1107312825U, // DSRL32 2355 0U, // DSRL32
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